MAX5970ETX+ Maxim Integrated Products, MAX5970ETX+ Datasheet - Page 27

• Manufacturer Part Number: MAX5970ETX+
• Description: IC CTLR HOT-SWAP DUAL 36TQFN
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5970ETX+

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 16 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0V to 16V, Dual Hot-Swap Controller with 10-Bit
The PG_ output for a given channel is asserted when
the voltage at MON_ is between the undervoltage and
overvoltage critical limits. The status of the power-good
signals is maintained in register status3[3:0]. A value of
Table 30. status3 Register Format
Table 31a. Power-Good Assertion Delay-Time Register Format
Table 31b. Power-Good Assertion Delay
The POL input sets the value of status3[5], which is a
read-only bit; the state of the POL input can be changed
at any time during operation and the polarity of the PG_
outputs changes accordingly.
Description:
Register Title:
Register Address:
Description:
Register Title:
Register Address:
Current and Voltage Monitor and 4 LED Drivers
bit 7
bit 7
—
—
R
R
pgdly1 (CH_)
Power-Good Detection and PG_ Outputs
0
0
1
1
RETRY
______________________________________________________________________________________
bit 6
bit 6
—
R
R
Power-good status register; LATCH, POL, ALERT and Power Good bits
status3
0x34
Power-good assertion delay-time register
pgdly
0x38
POL
bit 5
bit 5
—
R
R
pgdly0 (CH_)
0
1
0
1
ALERT
bit 4
R/W
bit 4
—
R
pgdly1
(CH1)
bit 3
bit 3
R/W
R
1 in any of the pg[] bits indicates a power-good condi-
tion, regardless of the POL setting, which only affects the
PG_ output polarity. The open-drain PG_ output can be
configured for active-high or active-low status indication
by the state of the POL input (see Table 30).
The assertion of the PG_ output is delayed by a user-
selectable time delay of 50ms, 100ms, 200ms, or 400ms
(see Tables 31a and 31b).
pgdly0
(CH1)
bit 2
R/W
bit 2
PG_ ASSERTION DELAY (ms)
R
pgdly1
(CH0)
pg[1]
100
200
400
bit 1
bit 1
50
R/W
R
pgdly0
(CH0)
pg[0]
bit 0
bit 0
R/W
R
VALUE
RESET
VALUE
RESET
0x00
0x00
27