LM3401MM/NOPB National Semiconductor, LM3401MM/NOPB Datasheet - Page 9

• Manufacturer Part Number: LM3401MM/NOPB
• Description: IC LED DRIVER HIGH BRIGHT 8-MSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: HBLED Driverr

Specifications of LM3401MM/NOPB

• Constant Current: Yes
• Topology: PWM, Step-Down (Buck)
• Number Of Outputs: 1
• Internal Driver: No
• Type - Primary: General Purpose
• Type - Secondary: High Brightness LED (HBLED)
• Frequency: 1.5MHz
• Voltage - Supply: 4.5 V ~ 35 V
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 1A
• Internal Switch(s): Yes
• Efficiency: 92%
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Number Of Segments: 1
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Package Type: MSOP
• Pin Count: 8
• Mounting: Surface Mount
• Power Dissipation: 660mW
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 35V
• For Use With: LM3401EVAL - BOARD EVALUATION FOR LM3401
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Compliant
• Other names: LM3401MMTR

switching noise can adversely affect the SNS or DIM pins. A
small capacitor for noise reduction will have little to no effect
on the LED ripple current or dimming but may help solve po-
tential EMI problems.
HG AND PFET SELECTION
When switching, the HG pin swings from V
below V
pin is below the upper threshold, HG will stay low, driving the
PFET on.
The PFET should be selected based on the maximum Drain-
Source voltage (V
Gate-Source voltage (V
capacitance.
The voltage across the PFET in the off state is equal to the
sum of the input voltage and the diode forward voltage. The
V
yond this voltage.
Since the peak current through the PFET is equal to the peak
current through the inductor, Id must be rated higher than the
maximum I
cle, therefore, the PFET drain current should be rated to
handle I
I
Although the typical HG voltage is V
go much lower during the initial PFET turn-on time. How far
HG swings at turn-on depends on several factors including
the gate capacitance, on-time, and input voltage. As shown
in the Typical Performance Characteristics, the initial HG volt-
age swing increases with decreasing PFET gate capacitance.
Therefore, A PFET must be selected with a maximum V
rating larger than the initial HG voltage. Conversely, when
driving PFETs with larger gate capacitance, the initial HG
voltage will be lower. In some cases, a low V
PFET may be required to ensure complete turn-on. Use the
Typical Performance curve as a guideline to selecting a prop-
er PFET.
Note that HG will eventually settle around the typical voltage
of V
HG has an absolute minimum voltage of 1.2V typically. When
the input voltage is below approximately 6V, this minimum
limit causes a reduction in drive voltage. At 5V input, for ex-
ample, HG will swing to 1.2V (or a gate drive voltage of -3.8V).
This may not be sufficient to drive some PFETs, and at this
reduced HG voltage, R
current limit. Therefore, a low V
recommended for lower input voltage applications.
The power loss in the PFET consists of switching losses and
conducting losses. Although switching losses are difficult to
precisely calculate, the equations below can be used to esti-
mate total power dissipation, which is the sum of PD
PD
Where P
D is the duty cycle. A value of 10 ns to 50 ns is typical for t
and t
ciency and accuracy.
Increasing R
ficiency. FET
125°C, the R
PK
DS
SW
= I
IN
must therefore be selected to provide some margin be-
off
.
AVE
- 4.7V regardless of the PFET gate capacitance.
. Longer PFET on and off times will degrade both effi-
IN
LED_PK
on
.
(typical). As long as the DIM pin is high and the SNS
= PFET turn-on time, P
LED_PK
DS(on)
DS(on)
RDS(on)
PD
continuously. In this case there is no ripple, so
FET_COND
. The LM3401 is capable of 100% duty cy-
will increase power losses and degrade ef-
may be as much as 150% higher than the
DS
has a positive temperature coefficient. At
), Drain current rating (Id), maximum
GS
DS(on)
), on-resistance (R
= R
is likely to increase and trigger
DS(on)
GS
off
IN
= PFET turn-off time, and
x I
threshold PFET is also
- 4.7V, this voltage can
LED
IN
2
x D
(off state) to 4.7V
DS(on)
GS
), and Gate
threshold
COND
and
GS
on
9
value at 25°C. The Gate capacitance of the PFET has a direct
impact on both PFET transition time and the power dissipation
in the LM3401. Most of the power dissipated in the LM3401
is used to drive the PFET switch. This power can be calcu-
lated as follows:
The average amount of gate driver current required during
switching (I
Where Q
And the total power dissipated in the IC is:
Where Iq is typically 1.05 mA and 4.7V is the typical HG volt-
age.
Maximum power dissipation within the LM3401 is limited by
ambient temperature. Use the following equation to deter-
mine maximum allowable power dissipation, or maximum
allowable ambient temperature:
Where θ
general, keeping the gate capacitance below 2000 pF is rec-
ommended to keep propagation delay, switching losses, and
power losses low. PFETs with very fast rise times may cause
excessive ringing at the HG node when combined with the
inductance of a long HG trace. To reduce this ringing, a small
resistor can be added between HG and the PFET gate. A
typical value of 10Ω is usually sufficient.
CURRENT LIMIT OPERATION
The LM3401 current limit monitors inductor current at each
switching cycle. Current is sensed across the R
PFET at the CS pin. When the PFET current exceeds the
current limit threshold, HG is turned off and the current limit
latch is set. In current limit mode, the PFET is held off until the
inductor current falls to near zero.
The current limit threshold is adjusted with a setting resistor,
shown as R3 in the typical application schematic, connected
from I
An internal 5.5 µA (typical) current sink at the ILIM pin creates
a voltage across the setting resistor. This voltage is compared
LIM
FIGURE 6. Typical Current Limit Operation
JA
g
to the V
is the PFET gate charge.
G
is the typical thermal resistance of 151°C/W. In
) is:
PD = (Iq x V
IN
node of the PFET.
I
G
= Q
IN
g
) + (I
x f
SW
G
x 4.7V)
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DS(on)
of the