LP3958TL/NOPB National Semiconductor, LP3958TL/NOPB Datasheet - Page 18

• Manufacturer Part Number: LP3958TL/NOPB
• Description: IC LED DRVR WT/CLR BCKLT 25-USMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Backlight, White LED, Color LEDr

Specifications of LP3958TL/NOPB

• Constant Current: Yes
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 5
• Internal Driver: Yes
• Type - Primary: Backlight, Light Management Unit (LMU)
• Type - Secondary: White LED
• Frequency: 1MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Voltage - Output: 18V
• Mounting Type: Surface Mount
• Package / Case: 25-MicroSMD
• Operating Temperature: -30°C ~ 85°C
• Internal Switch(s): Yes
• Efficiency: 90%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Other names: LP3958TLTR

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Symbol
LOGIC INPUT SCL, SDA, GPIO[0:2]
V
V
I
f
LOGIC INPUT NRST
V
V
I
t
LOGIC OUTPUT SDA
V
V
I
LOGIC OUTPUT GPIO[0:2]
V
V
I
I
SCL
I
NRST
L
L
General Purpose I/O Functionality
LP3958 has three general purpose I/O pins: GPIO[0]/PWM,
GPIO[1] and GPIO[2]. GPIO[0]/PWM can also be used as a
PWM input for the external LED PWM controlling. GPIO
bi-directional drivers are operating from the V
domain.
Registers for GPIO are as follows:
Logic Interface Characteristics
(V
IL
IH
IL
IH
OL
OH
OL
OH
DDIO
EN_PWM_PIN
OEN[2:0]
= 1.65V...V
Name
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
Input Low Level
Input High Level
Input Current
Reset Pulse Width
Output Low Level
Output High Level
Output Leakage Current
Output Low Level
Output High Level
Output Leakage Current
GPIO CONTROL (06H)
Parameter
DD1,2
unless otherwise noted)
2:0
Bit
4
Enable PWM pin
0 = disable
1 = enable
GPIO pin direction
0 = input
1 = output
I
I
V
I
I
V
SDA
SDA
GPIO
GPIO
Conditions
Description
SDA
GPIO
= 3mA
= -3mA
= 2.8V
= 3 mA
= −3 mA
= 2.8V
DDIO
supply
V
V
18
0.8xV
DDIO
DDIO
−1.0
Min
-1.0
1.2
10
GPIO control register is used to set the direction of each
GPIO pin. For example, by setting OEN0 bit high the
GPIO[0]/PWM pin acts as a logic output pin with data de-
fined DATA0 in GPIO data register. Note, that the EN_PW-
M_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to
act as PWM input. GPIO[1] and GPIO[2] pins can be se-
lected to be inputs or outputs, defined by OEN1 and OEN2
bit status. PWM functionality is valid only for GPIO[0]/PWM
pin. GPIO data register contains the data of GPIO pins.
When output direction is selected to GPIO pin, then GPIO
data register defines the output pin state. When GPIO data
register is read, it contains the state of the pin despite of the
pin direction.
DDIO
− 0.5
− 0.5
DATA[2:0]
Name
V
V
DDIO
DDIO
GPIO DATA (07H)
Typ
0.3
0.3
− 0.3
− 0.3
Bit
2:0
0.2xV
Max
400
1.0
0.5
1.0
0.5
1.0
0.5
1.0
Data bits
DDIO
Description
Units
kHz
µA
µA
µA
µA
µs
V
V
V
V
V
V
V