LM3502SQX-16/NOPB National Semiconductor, LM3502SQX-16/NOPB Datasheet - Page 2

• Manufacturer Part Number: LM3502SQX-16/NOPB
• Description: IC LED DRIVR WHITE BCKLGT 16-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Backlight, White LEDr

Specifications of LM3502SQX-16/NOPB

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 2
• Internal Driver: Yes
• Type - Primary: Backlight
• Type - Secondary: White LED
• Frequency: 800kHz ~ 1.2MHz
• Voltage - Supply: 2.5 V ~ 5.5 V
• Voltage - Output: 15 V ~ 15.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-LLP
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 400mA
• Internal Switch(s): Yes
• Efficiency: 80%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM3502SQX-16

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Bump #
Connection Diagrams
Pin Descriptions/Functions
Cntrl (Bump A1): Shutdown control pin. When V
1.4V, the LM3502 is enabled or ON. When V
the LM3502 will enter into shutdown mode operation. The
LM3502 has an internal pull down resistor on the Cntrl pin,
thus the device is normally in the off state or shutdown mode
of operation.
Fb (Bump B1): Output voltage feedback connection. The
white LED string network current is set/programmed using a
resistor from this pin to ground.
V
and NMOS FET switches. (Figure 2: P1 and N2). It is rec-
ommended to connect 100nF at V
and LM3502-44 versions if V
V
FET switch (Figure 2: P1) and OVP sensing node. The
output capacitor must be connected as close to the device
OUT2
OUT1
A1
B1
C1
D1
D2
D3
C3
B3
A3
A2
(Bump D1): Source connection of the internal PMOS
(Bump C1): Drain connections of the internal PMOS
15 and 16
2 and 3
Pin #
DAP
14
13
12
10
11
9
7
6
4
1
5
8
10-Bump Thin MicroSMD
Package (TLP10)
TOP VIEW
PGND
AGND
V
V
Name
OUT2
Cntrl
DAP
En2
En1
OUT2
OUT1
Sw
V
NC
NC
NC
NC
Fb
IN
OUT2
is not used.
Shutdown Control Connection
Feedback Voltage Connection
Drain Connections of The NMOS and PMOS Field Effect Transistor (FET) Switches
(Figure 2: N2 and P1)
Over-Voltage Protection (OVP) and Source Connection of The PMOS FET Switch
(Figure 2: P1)
Drain Connection of The Power NMOS Switch (Figure 2: N1)
Power Ground Connection
Analog Ground Connection
Supply or Input Voltage Connection
NMOS FET Switch Control Connection
PMOS FET Switch Control Connection
No Connection
No Connection
No Connection
No Connection
Die Attach Pad (DAP), must be soldered to the printed circuit board’s ground plane for
enhanced thermal dissipation.
for the LM3502-35V
20131702
Cntrl
is ≤ 0.3V,
Cntrl
is ≥
2
as possible, between the V
connect the Schottky diode as close as possible to the
V
Sw (Bump D2): Drain connection of the internal power
NMOS FET switch. (Figure 2: N1) Minimize the metal trace
length and maximize the metal trace width connected to this
pin to reduce EMI radiation and trace resistance.
PGND (Bump D3): Power ground pin. Connect directly to
the ground plane.
AGND (Bump C3): Analog ground pin. Connect the analog
ground pin directly to the PGND pin.
V
C
between the V
En2 (Bump A3): Enable pin for the internal NMOS FET
switch (Figure 2: N2) during device operation. When V
OUT1
IN
IN
(Bump B3): Supply or input voltage connection pin. The
capacitor should be as close to the device as possible,
pin to minimize trace resistance and EMI radiation.
Description
16-Lead Thin Leadless Leadframe
IN
pin and ground plane.
Package (SQA16A)
TOP VIEW
OUT1
pin and ground plane. Also
20131703
En2
is