MAX7306ALB+T Maxim Integrated Products, MAX7306ALB+T Datasheet - Page 18

• Manufacturer Part Number: MAX7306ALB+T
• Description: IC LED DRIVER LINEAR 10-UDFN
• Manufacturer: Maxim Integrated Products
• Type: Linear (I²C Interface)r

Specifications of MAX7306ALB+T

• Topology: PWM
• Number Of Outputs: 4
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: White LED
• Frequency: 1MHz
• Voltage - Supply: 1.62 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 10-µDFN
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 25mA
• Internal Switch(s): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Details

The MAX7306/MAX7307 operate as a slave that sends
and receives data through an I
interface. The interface uses a serial-data line (SDA)
and a serial-clock line (SCL) to achieve bidirectional
communication between master(s) and slave(s). A
master (typically a microcontroller) initiates all data
transfers to and from the MAX7306/MAX7307 and gen-
erates the SCL clock that synchronizes the data trans-
fer (see Figure 8).
The MAX7306/MAX7307 SDA line operates as both an
input and an open-drain output. A 4.7kΩ (typ) pullup
resistor is required on SDA. The MAX7306/MAX7307
SCL line operates only as an input. A 4.7kΩ (typ) pullup
resistor is required on SCL if there are multiple masters
on the 2-wire interface, or if the master in a single-mas-
ter system has an open-drain SCL output.
Each transmission consists of a START condition (see
Figure 9) sent by a master, followed by the MAX7306/
MAX7307 7-bit slave address plus R/W bit, a register
address byte, one or more data bytes, and finally a STOP
condition (see Figure 9).
SMBus/I
GPIOs and LED Drivers
Figure 8. 2-Wire Serial Interface Timing Details
Figure 9. Start and Stop Conditions
18
SDA
SCL
______________________________________________________________________________________
CONDITION
START
S
RESET
SDA
SCL
t
HD,STA
START CONDITION
2
C Interfaced 4-Port, Level-Translating
t
LOW
Serial Interface
Serial Addressing
2
t
C-compatible, 2-wire
R
t
SU,DAT
t
HIGH
t
F
t
HD,DAT
CONDITION
STOP
P
t
REPEATED START CONDITION
SU,STA
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 9).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(see Figure 10).
The acknowledge bit is a clocked 9th bit that the recipient
uses to acknowledge receipt of each byte of data (see
Figure 11). Thus, each effectively transferred byte
requires 9 bits. The master generates the 9th clock pulse,
and the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the high
period of the clock pulse. When the master is transmitting
to the MAX7306/MAX7307, the devices generate the
acknowledge bit because the MAX7306/MAX7307 are the
Figure 10. Bit Transfer
SDA
SCL
t
WL(RST)
t
HD,STA
DATA LINE STABLE;
DATA VALID
t
CHANGE OF DATA
SU,STO
START and STOP Conditions
ALLOWED
CONDITION
STOP
t
BUF
CONDITION
START
Acknowledge
Bit Transfer