A6277ELW-T Allegro Microsystems Inc, A6277ELW-T Datasheet - Page 6

• Manufacturer Part Number: A6277ELW-T
• Description: IC LED DRIVER LINEAR 20-SOIC
• Manufacturer: Allegro Microsystems Inc
• Type: Linear (Non-Switching)r

Specifications of A6277ELW-T

• Constant Current: Yes
• Topology: 8-Bit Shift Register
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: General Purpose
• Frequency: 20MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Voltage - Output: 1V
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 120mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Other names: 620-1087

A6277
A. Data Active Time Before Clock Pulse
B. Data Active Time After Clock Pulse
C. Clock Pulse Width, t
D. Time Between Clock Activation
E. Latch Enable Pulse Width, t
F. Output Enable Pulse Width, t
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
— Max. Clock Transition Time, t
(Data Set-Up Time), t
(Data Hold Time), t
and Latch Enable, t
w(CK)
su(L)
h(D)
su(D)
............................................... 50 ns
.............................................. 20 ns
............................................ 100 ns
w(L)
DATA OUT.
DATA OUT.
.......................................... 60 ns
w(OE)
TIMING REQUIREMENTS and SPECIFICATIONS
OUTPUT
ENABLE
r
ENABLE
DATA IN
SERIAL
SERIAL
OUTPUT
ENABLE
CLOCK
SERIAL
LATCH
or t
................................... 100 ns
OUT
8-Bit Serial Input Constant-Current Latched LED Driver
OUT
................................ 4.5 s
f
N
1
2
.............................. 10 s
N
A
DATA
(Logic Levels are V
50%
B
t
50%
p
C
50%
LOW = ALL OUTPUTS ENABLED
D
50%
F
t
t
pHL
p
50%
DD
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
HIGH = ALL OUTPUTS DISABLED (BLANKED)
and Ground)
50%
E
Information present at any register is transferred to the
When the OUTPUT ENABLE input is high, the output
90%
t
p
t
pLH
DATA
DATA
t
DATA
f
50%
HIGH = OUTPUT OFF
LOW = OUTPUT ON
t
r
Dwg. WP-030-1A
10%
Dwg. WP-029-3
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
50%
DATA
5