STP08CDC596B1 STMicroelectronics, STP08CDC596B1 Datasheet

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... Consequently, choosing this device does not mean to change the footprint on the board. Order codes Part Number Temperature range STP08CDC596B1 -40°C to 125°C STP08CDC596M -40°C to 125°C STP08CDC596MTR -40°C to 125°C STP08CDC596TTR -40°C to 125°C STP08CDC596XTTR -40° ...

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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STP08CDC596 1 Summary description Table 1. Current accuracy Output voltage ≥0.7V 1.1 Pin connection and description Figure 1. Connections diagram Table 2. Pin description PIN N° 5- Current accuracy Between bits (Typ) ...

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Block diagram 2 Block diagram Figure 2. Block diagram 4/29 STP08CDC596 ...

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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 3.1 Absolute maximum ratings Table 3 ...

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Maximum rating 3.3 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V Supply voltage DD V Output voltage O I Output current O I Output current OH I Output current OL V Input voltage IH V Input voltage ...

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STP08CDC596 4 Electrical characteristics Table 6. Electrical characteristics (V Symbol Parameter V Input voltage high level IH V Input voltage low level IL I Output leakage current OH V Output voltage (Serial-OUT Output voltage (Serial-OUT OL1 ...

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Switching characteristics 5 Switching characteristics Table 7. Switching Characteristics (V Symbol Parameter Propagation delay time, t CLK-OUTn, LE/DM1 = H, PLH1 OE/DM2 = L Propagation delay time, t PLH2 LE/DM1-OUTn, OE/DM2 = L Propagation delay time, t PLH3 OE/DM2-OUTn, LE/DM1 ...

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STP08CDC596 6 Equivalent circuit of inputs and outputs Figure 3. OE terminal Figure 4. LE terminal Figure 5. CLK, SDI terminal Equivalent circuit of inputs and outputs 9/29 ...

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Equivalent circuit of inputs and outputs Figure 6. SDO terminal 10/29 STP08CDC596 ...

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STP08CDC596 7 Timing diagram Figure 7. Timing diagram Note: In normal mode the OE/DM2 must remain low at least two clock cycles. In case of OE signal enabled (OE = LOW) during no clock activity (clock stopped), after the CLK ...

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Timing diagram Figure 8. Clock, serial-in, serial-out Figure 9. Clock, serial-in, latch, enable, outputs 12/29 STP08CDC596 ...

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STP08CDC596 Figure 10. Outputs Timing diagram 13/29 ...

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Test circuit 8 Test circuit Figure 11. DC characteristics Figure 12. AC characteristics 14/29 STP08CDC596 ...

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STP08CDC596 Figure 13. Timing example for open and/or short detection Test circuit 15/29 ...

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Running the detection mode 9 Running the detection mode 9.1 Phase one: “entering in detection mode“ From the “Normal Mode” condition the device can switch to the “Error Mode“ logic sequence on the OE/DM2 and LE/DM1 pins as ...

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STP08CDC596 9.2 Phase two: “error detection“ The eight data bits must be set “1“ in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the ...

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Running the detection mode 9.3 Phase three: “resuming to normal mode” The sequence for re-entering in normal mode is showed in the following Table and diagram: Table 11. Resuming to normal mode timing diagram CLK OE/DM2 LE/DM1 Table 12. Resuming ...

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STP08CDC596 9.4 Condition in order to get a successfully detection condition Table 13. Detection condition (V SW-1 or SW-3b SW-2 or SW-3a Note: Where the output current programmed by the R O current in detection mode. Figure 14. ...

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Typical characteristics 10 Typical characteristics Figure 15. Output current-REXT resistor Figure 16. Dropout voltage vs output Figure 17. Power dissipation vs temperature package 20/29 STP08CDC596 current Figure 18. Output current vs ±∆I (%) OL ...

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STP08CDC596 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...

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Package mechanical data DIM. MIN. a1 0. 22/29 Plastic DIP-16 (0.25) MECHANICAL DATA mm. TYP MAX. 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 STP08CDC596 ...

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STP08CDC596 DIM. MIN 0 0. 9 3.8 G 4 SO-16 MECHANICAL DATA mm. TYP MAX. 1.75 0.25 0.004 1.64 0.46 0.013 0.25 ...

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Package mechanical data DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 4.9 E 6 0˚ PIN 1 IDENTIFICATION 1 24/29 TSSOP16 MECHANICAL DATA mm. TYP MAX. ...

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STP08CDC596 TSSOP16 EXPOSED PAD MECHANICAL DATA DIM. MIN 0.8 b 0.19 c 0.09 D 4.9 D1 1.7 E 6.2 E1 4 0° L 0.45 mm. TYP MAX. MIN. 1.2 0.15 1 1.05 0.031 ...

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Package mechanical data Tape & Reel TSSOP16 MECHANICAL DATA DIM. MIN 12 6.7 Bo 5.3 Ko 1.6 Po 3.9 P 7.9 26/29 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 22.4 ...

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STP08CDC596 DIM. MIN 12 6.45 Bo 10.3 Ko 2.1 Po 3.9 P 7.9 Tape & Reel SO-16 MECHANICAL DATA mm. TYP MAX. 330 13.2 22.4 6.65 10.5 2.3 4.1 8.1 Package mechanical ...

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Revision history 12 Revision history Table 1. Revision history Date 15-Jun-2005 11-Oct-2005 2-Aug-2006 28/29 Revision 1 First release 2 Minor revision, no content change New template, block diagram 3 equivalent circuit Section 6 on page 9 TSSOP-16 Exposed Pad package. ...

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... STP08CDC596 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...