LTC3900ES8 Linear Technology, LTC3900ES8 Datasheet - Page 8

• Manufacturer Part Number: LTC3900ES8
• Description: IC DRIVER RECT SYNC CONV 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC3900ES8

• Configuration: High-Side
• Input Type: Inverting and Non-Inverting
• Delay Time: 60ns
• Current - Peak: 2A
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 11 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• High Side Voltage - Max (bootstrap): -

LTC3900
APPLICATIONS INFORMATION
The timer circuit and current sense comparator in LTC3900
are used to prevent reverse current buildup in the output
inductor.
Timer
Figure 3 shows the LTC3900 timer internal and external
circuits. The timer operates by using an external R-C
charging network to program the time-out period. On
every negative transition at the SYNC input, the chip
generates a 200ns pulse to reset the timer cap. If the
SYNC signal is missing or incorrect, allowing the timer
cap voltage to go high, it shuts off both drivers once the
voltage reaches the time-out threshold. Figure 4 shows
the timer waveforms.
A typical forward converter cycle always turns on Q3
and Q4 alternately and the SYNC input should alternate
between positive and negative pulses. The LTC3900 timer
also includes sequential logic to monitor the SYNC input
sequence. If after one negative pulse, the SYNC compara-
tor receives another negative pulse, the LTC3900 will not
reset the timer cap. If no positive SYNC pulse appears,
both drivers are shut off once the timer times out. Once
positive pulses reappear the timer resets and the drivers
start switching again. This is to protect the external com-
ponents in situations where only negative SYNC pulse is
present and FG output remains high. Figure 5 shows the
timer waveforms with incorrect SYNC pulses.
The LTC3900 has two separate SYNC comparators (S
S
pulses. The threshold voltages of both comparators are
8
–
in the Block Diagram) to detect the positive and negative
TIMEOUT
TIMER
RESET
Figure 3. Timer Circuit
TMR
R2
R1
Z
TMR
3900 F03
4
7
V
CC
R
TMR
C
TMR
+
and
designed to be of the same magnitude (1.4V typical) but
opposite in polarity. In some situations, for example dur-
ing power up or power down, the SYNC pulse magnitude
may be low, slightly higher or lower than the threshold of
the comparators. This can cause only one of the SYNC
comparators to trip. This also appears as incorrect SYNC
pulse and the timer will not reset.
The timeout period is determined by the external R
and C
This is achieved by making the timeout threshold a ratio
of V
Figure 3). The timeout period should be programmed to
be around one period of the primary switching frequency
using the following formula:
To reduce error in the timeout setting due to the discharge
time, select C
C
C
with minimum PCB trace between C
and GND. This is to reduce any ringing caused by the PCB
trace inductance when C
introduce error to the timeout setting.
The timer input also includes a current sinking clamp
circuit (Z
0.5 • V
clamp circuit prevents the timer cap from getting fully
charged up to the rail, which results in a longer discharge
TMR
TMR
TIMEOUT = 0.2 • R
TIMER RESET
CC
(INTERNAL)
should be placed as close as possible to the LTC3900
around 470pF and then calculate the required R
TMR
. The ratio is 0.2x, set internally by R1 and R2 (see
CC
TIMER
SYNC
TMR
if there is missing SYNC/timer reset pulse. This
FG
CG
SG
values and is independent of the V
TMR
in Figure 3) that clamps this pin to about
Figure 4. Timer Waveforms
between 100pF and 1000pF . Start with a
TMR
TMR
• C
discharges. This ringing may
TMR
+ 0.27E-6
TMR
, the TIMER pin
THRESHOLD
CC
TIMEOUT
LAST
PULSE
voltage.
3900 F04
TMR
3900fa
TMR
.