A3985SLDTR-T Allegro Microsystems Inc, A3985SLDTR-T Datasheet - Page 15
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A3985SLDTR-T
Manufacturer Part Number
A3985SLDTR-T
Description
IC MOSFET DRVR PROG DUAL 38TSSOP
Manufacturer
Allegro Microsystems Inc
Datasheet
1.A3985SLDTR-T.pdf
(15 pages)
Specifications of A3985SLDTR-T
Configuration
H Bridge
Input Type
Non-Inverting
Delay Time
120ns
Number Of Configurations
2
Number Of Outputs
8
Voltage - Supply
12 V ~ 50 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
38-TSSOP
Device Type
Full Bridge
Module Configuration
Full Bridge
Peak Output Current
500nA
Output Resistance
19ohm
Input Delay
120ns
Output Delay
120ns
Supply Voltage Range
12V To 50V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Peak
-
High Side Voltage - Max (bootstrap)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
620-1180-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3985SLDTR-T
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
A3985
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright ©2005-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
38X
0.10
0.22 ±0.05
C
38
1
2
A
9.70 ±0.10
0.50
For the latest version of this document, visit our website:
LD Package, 38-Pin TSSOP
4.40 ±0.10
0.10 ±0.05
www.allegromicro.com
SEATING
PLANE
1.20 MAX
C
6.40 ±0.20
Dual Full-Bridge MOSFET Driver
GAUGE PLANE
0.25
4º
SEATING PLANE
0.15
+0.06
–0.05
Digitally Programmable
A Terminal #1 mark area
B
All dimensions nominal, not for tooling use
(reference JEDEC MO-153 BD-1)
Dimensions in millimeters
38
1
Reference pad layout (reference IPC SOP50P640X110-38M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
1.60
2
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
B
PCB Layout Reference View
0.50
0.30
6.00
15