PM8834 STMicroelectronics, PM8834 Datasheet - Page 12

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PM8834

Manufacturer Part Number
PM8834
Description
IC MOSFET DVR 4A DUAL SOIC-8
Manufacturer
STMicroelectronics
Type
Low Side Mosfet Driverr
Datasheet

Specifications of PM8834

Configuration
Low-Side
Input Type
PWM
Delay Time
35ns
Current - Peak
4A
Number Of Configurations
2
Number Of Outputs
2
Voltage - Supply
5 V ~ 18 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Product
Driver ICs - Various
Rise Time
10 ns
Fall Time
10 ns
Propagation Delay Time
45 ns
Supply Voltage (max)
18 V
Supply Voltage (min)
4.5 V
Supply Current
3.5 mA
Maximum Power Dissipation
1.4 W
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Number Of Drivers
2
Output Current
500 mA
Output Voltage
10 V
Wide Input Supply Voltage Range
5 V to 18 V
Wide Operative Temperature Range
-40 °C to 105 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Design guidelines
5.3
12/18
Figure 6.
Layout guidelines
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (also EMI and losses) power connections must be a part
of a power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized.
Traces between the driver and the MOSFETS should be short and wide to minimize the
inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count
needs to be minimized to reduce the related parasitic effect.
Small signal components and connections to critical nodes of the application as well as
bypass capacitors for the device supply are also important. Locate the bypass capacitor
(VCC capacitors) close to the device with the shortest possible loop and use wide copper
traces to minimize parasitic inductance.
To improve heat dissipation, place copper area under the IC. This copper area may be
connected with other layers (if available) through VIAs to improve the thermal conductivity.
Figure 7.
Equivalent circuit for MOSFET drive
Power dissipation estimation
(single channel) for
capacitive load of 10 nF with
no gate resistor
Doc ID 15086 Rev 2
Figure 8.
Power dissipation estimation
(single channel) for
capacitive load of 10 nF with
4.7 Ω gate resistor
PM8834

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