MAX8791BGTA+ Maxim Integrated Products, MAX8791BGTA+ Datasheet - Page 9

• Manufacturer Part Number: MAX8791BGTA+
• Description: IC MOSF DRIVER 1PH SYNCH 8TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8791BGTA+

• Configuration: High and Low Side, Synchronous
• Input Type: Differential
• Delay Time: 14ns
• Current - Peak: 2.7A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 4.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 8-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

V
cuits. Bypass V
tor to GND to limit noise to the internal circuitry. Connect
these bypass capacitors as close as possible to the IC.
When V
are held low. Once V
and while PWM is low, DL is driven high and DH is
driven low. This prevents the output of the converter
from rising before a valid PWM signal is applied.
The MAX8791/MAX8791B enter into low-power pulse-
skipping mode when SKIP is pulled low. In skip mode,
an inherent automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. A zero-
crossing comparator truncates the low-side switch on-
time at the inductor current’s zero crossing. The
comparator senses the voltage across LX and GND.
Once V
parator threshold (see the Electrical Characteristics ),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-cur-
rent operation. The PFM/PWM crossover occurs when
the load current of each phase is equal to 1/2 the peak-
to-peak ripple current, which is a function of the induc-
tor value. For a battery input range of 7V to 20V, this
threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The switching waveforms may appear
noisy and asynchronous when light loading activates
the pulse-skipping operation, but this is a normal oper-
ating condition that results in high light-load efficiency.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention. The
high-side MOSFET (N
resistive losses plus the switching losses at both
V
Ideally, the losses at V
to losses at V
the losses at V
losses at V
(reducing R
if the losses at V
DD
IN(MIN)
provides the supply voltage for the internal logic cir-
LX
DD
Single-Phase, Synchronous MOSFET Drivers
and V
- V
IN(MAX)
is below the UVLO threshold, DH and DL
DS(ON)
GND
IN(MAX)
DD
IN(MIN)
Applications Information
IN(MAX)
IN(MAX)
_______________________________________________________________________________________
, consider increasing the size of N
drops below the zero-crossing com-
with a 1µF or larger ceramic capaci-
but increasing C
Low-Power Pulse Skipping
, with lower losses in between. If
DD
H
Power-MOSFET Selection
IN(MIN)
are significantly higher than the
) must be able to dissipate the
. Calculate both these sums.
are significantly higher than the
Input Undervoltage Lockout
is above the UVLO threshold
5V Bias Supply (V
should be roughly equal
GATE
). Conversely,
DD
H
)
losses at V
(increasing R
not vary over a wide range, the minimum power dissi-
pation occurs where the resistive losses equal the
switching losses. Choose a low-side MOSFET that has
the lowest possible on-resistance (R
a moderate-sized package (i.e., one or two 8-pin SOs,
DPAK, or D2PAK), and is reasonably priced. Ensure
that the DL gate driver can supply sufficient current to
support the gate charge and the current injected into
the parasitic gate-to-drain capacitor caused by the
high-side MOSFET turning on; otherwise, cross-con-
duction problems can occur.
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
case power dissipation due to resistance occurs at the
minimum input voltage:
where η
a small high-side MOSFET is desired to reduce switch-
ing losses at high input voltages. However, the R
required to stay within package-power dissipation often
limits how small the MOSFETs can be. Again, the opti-
mum occurs when the switching losses equal the con-
duction (R
do not usually become an issue until the input is
greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N
it must allow for difficult quantifying factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics.
The following switching-loss calculation provides only a
very rough estimate and is no substitute for prototype
evaluation, preferably including verification using a
thermocouple mounted on N
where C
Q
MOSFET, and I
current (5A typ).
PD N
G(SW)
PD N
(
(
H
TOTAL
is the charge needed to turn on the high-side
OSS
H
SWITCHING
DS(ON)
IN(MIN)
RESISTIVE
H
is the N
DS(ON)
) due to switching losses is difficult since
is the total number of phases. Generally,
GATE
) losses. High-side switching losses
, consider reducing the size of N
MOSFET Power Dissipation
)
but reducing C
is the peak gate-drive source/sink
H
=
)
=
⎛
⎜
⎝
MOSFET’s output capacitance,
C
V
⎛
⎜
⎝
IN MAX LOAD SW
OSS IN SW
V
OUT
V
(
H
IN
V
n
:
2
TOTAL
⎞
⎟
⎠
)
2
I
⎛
⎜
⎝
f
η
I
LOAD
TOTAL
GATE
DS(ON)
f
H
⎞
⎟
⎠
). If V
⎞
⎟
⎠
⎛
⎜
⎝
), the worst-
2
), comes in
Q
I
R
GATE
G SW
DS ON
(
IN
DS(ON)
(
)
does
⎞
⎟ +
⎠
)
9
H