IR2112S International Rectifier, IR2112S Datasheet - Page 2

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IR2112S

Manufacturer Part Number
IR2112S
Description
IC MOSFET DRVR HI/LO SIDE 16SOIC
Manufacturer
International Rectifier
Datasheet

Specifications of IR2112S

Configuration
High and Low Side, Independent
Input Type
Non-Inverting
Delay Time
125ns
Current - Peak
250mA
Number Of Configurations
1
Number Of Outputs
2
High Side Voltage - Max (bootstrap)
600V
Voltage - Supply
10 V ~ 20 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*IR2112S

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Note 1: Logic operational for V
DT97-3 for more details).
Note 2: When V
IR2112 ( -1-2 )( S ) PbF
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V S and V SS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in Figures 36 and 37.
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
2
Symbol
Symbol
R
dV
V
V
V
V
V
V
V
V
V
V
V
V
THJA
V
V
P
V
V
T
T
T
T
HO
HO
CC
DD
CC
LO
DD
SS
LO
SS
s
IN
IN
A
B
S
D
S
L
B
S
J
/dt
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Ambient Temperature
High Side Floating Supply Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Allowable Offset Supply Voltage Transient (Figure 2)
Package Power Dissipation @ T
Thermal Resistance, Junction to Ambient
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
DD
< 5V, the minimum V
S
of -5 to +600V. Logic state held for V
SS
Definition
Definition
offset is limited to -V
A
+25°C
(16 Lead SOIC)
(16 Lead SOIC)
(14 Lead DIP)
(14 Lead DIP)
DD
.
S
of -5V to -V
-5 (Note 2)
V
V
BS
V
V
V
V
Note 1
SS
CC
Min.
Min.
S
S
SS
B
V
-0.3
-0.3
-0.3
-0.3
. (Please refer to the Design Tip
-40
-55
V
10
0
- 0.3
+ 10
SS
- 25
- 0.3
S
- 25
+ 3
V
V
V
V
V
V
V
V
CC
CC
DD
Max.
SS
Max.
SS
B
B
S
1.25
V
V
625
100
150
150
300
600
125
1.6
V
25
50
75
20
+ 0.3
+ 0.3
CC
5
DD
+ 20
+ 0.3
+ 0.3
+ 0.3
+ 25
B
+ 20
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Units
Units
°C/W
V/ns
°C
W
°C
V
V

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