FDMF6704 Fairchild Semiconductor, FDMF6704 Datasheet - Page 5

• Manufacturer Part Number: FDMF6704
• Description: IC DRMOS MODULE 1000KHZ 40-MLP
• Manufacturer: Fairchild Semiconductor
• Series: XS™ DrMOSr
• Type: High Side/Low Side Driverr

Specifications of FDMF6704

• Input Type: Non-Inverting
• Number Of Outputs: 1
• Current - Output / Channel: 35A
• Current - Peak Output: 80A
• Voltage - Supply: 3 V ~ 14 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Product: Driver ICs - Various
• Rise Time: 25 ns
• Fall Time: 20 ns
• Supply Voltage (min): 8 V
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Drivers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• On-state Resistance: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FDMF6704 Rev. G
Description of Operation
Circuit Description
The FDMF6704 is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 1 MHz.
PWM
When the PWM input goes high, the high side MOSFET turns
on. When it goes low, the low side MOSFET turns on. When it is
open, both the low side and high side MOFET will turn off.
The DISB# input is combined with the PWM signal to control the
driver output. In a typical multiphase design, DISB# will be a
shared signal used to turn on all phases. The individual PWM
signals from the controller will be used to dynamically enable or
disable individual phases.
Low-Side Driver
The low-side driver (GL) is designed to drive a ground
referenced low R
internally connected between VDRV and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB# = 0 V), GL
is held low.
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal diode and external bootstrap capacitor (C
start-up, VSWH is held at PGND, allowing C
V
high, GH will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from C
delivered to Q1's gate. As Q1 turns on, VSWH rises to V
forcing the BOOT pin to V
sufficient VGS enhancement for Q1. To complete the switching
cycle, Q1 is turned off by pulling GH to VSWH. C
recharged to VDRV when VSWH falls to PGND. GH output is in
phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
SMOD
The SMOD (Skip Mode) function allows for higher converter
efficiency under light load conditions. During SMOD, the LS
FET is disabled and it prevents discharging of output caps.
When the SMOD# pin is pulled high, the sync buck converter
will work in synchronous mode. When the SMOD# pin is pulled
low, the LS FET is turned off. The SMOD function does not have
internal current sensing. This SMOD# pin is connected to a
PWM controller which enables or disables the SMOD
automatically when the controller detects light load condition.
Normally this pin is Active Low.
DRV
through the internal diode. When the PWM input goes
DS(ON)
N-channel MOSFET. The bias for GL is
IN
+V
C(BOOT)
, which provides
BOOT
BOOT
BOOT
to charge to
BOOT
). During
is then
and
IN
,
5
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 4 for the
relevant timing waveforms.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the GL pin. When the PWM signal goes HIGH, Q2 will begin
to turn OFF after some propagation delay (t
pin is discharged below 1 V, Q1 begins to turn ON after adaptive
delay t
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the
VSWH pin. When the PWM signal goes LOW, Q1 will begin to
turn OFF after some propagation delay (t
VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive
delay t
Additionally, V
discharged low, a secondary adaptive delay is initiated, which
results in Q2 being driven ON after 250 ns
state. This function is implemented to ensure C
recharged each switching cycle, particularly for cases where the
power convertor is sinking current and VSWH voltage does not
fall below the 1 V adaptive threshold. The 250 ns secondary
delay is longer than t
DTHH
DTLH
.
.
GS
of Q1 is monitored. When V
DTLH
.
,
regardless of VSWH
PDLL
PDHL
). Once the GL
www.fairchildsemi.com
). Once the
GS(Q1)
BOOT
is
is