VN5770AK-E STMicroelectronics, VN5770AK-E Datasheet - Page 25

• Manufacturer Part Number: VN5770AK-E
• Description: IC SSR QUAD FOR H BRIDGE 28SOIC
• Manufacturer: STMicroelectronics
• Series: OMNIFET II™r
• Type: H Bridger

Specifications of VN5770AK-E

• Input Type: Non-Inverting
• Number Of Outputs: 4
• On-state Resistance: 160 mOhm
• Current - Output / Channel: 8.5A
• Voltage - Supply: 4.5 V ~ 36 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Peak Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

VN5770AK-E
Table 18.
Table 19.
1. values dependent on PCB heatsink area
Table 20.
1. values dependent on PCB heatsink area
Table 21.
1. Calculation is valid in any dynamic operating condition. Pd values set by user.
R
R
R
R
Z
Z
Z
Z
T
T
T
OFF
HS
ON
jHS12
jLS3
jLS4
thHS
thLS
thHSLS
thLSLS
thHS
thLS
thHSLS
thLSLS
1
= Z
= R
OFF
= R
HS
ON
= Z
= Z
= R
= R
thLS3
2
thLS3
thHS1
thLS3LS4
thHS12LS3
thLS3LS4
Thermal calculations in clockwise and anti-clockwise operation in steady-
state mode
Thermal resistances definitions
Single pulse thermal impedance definitions
Thermal calculations in transient mode
thHS1LS4
OFF
LS
ON
= Z
= R
3
= R
thLS4
thLS4
OFF
Z
Z
LS
thHS2
ON
Z
thHS
thHSLS
= R
thHSLS
= Z
4
thHS2LS3
thHS12LS4
P
R
P
R
x P
dHS1
dHS2
thHSLS
thHSLS
x P
x P
dHS12
x
x
dHS12
dHS12
R
R
+ T
+ T
T
thHS
thHS
jHS12
+ Z
amb
amb
High side chip thermal resistance junction to ambient
(HS
Low side chip thermal resistance junction to ambient
Mutual thermal resistance junction to ambient between
high side and low side chips
Mutual thermal resistance junction to ambient between
low side chips
High Side Chip Thermal Impedance Junction to
Ambient
Low Side Chip Thermal Impedance Junction to
Ambient
Mutual Thermal Impedance Junction to Ambient
between High Side and Low Side Chips
Mutual Thermal Impedance Junction to Ambient
between Low Side Chips
+ Z
+ Z
+ P
+ P
thHSLS
1
thLS
dLS4
dLS3
thLSLS
or HS
x P
x
x
x (P
(1)
2
x P
P
P
P
P
dLS3
in ON state)
dLS3
dHS1
dLS4
dHS2
dLS3
dLS3
+ Z
x
x
+ P
x
x
(1)
R
R
R
R
+ Z
T
thLSLS
thLSLS
thLS
thHSLS
thHSLS
jLS3
dLS4
(1)
thLS
+ T
) + T
+ T
x P
+
+
Package and thermal data
amb
x P
amb
amb
dLS4
dLS4
P
P
P
P
+ T
dHS1
dLS4
dHS2
dLS3
+ T
amb
amb
x
x
x
x
R
R
R
R
T
thLS
thLSLS
thHSLS
thHSLS
jLS4
+ T
+ T
+
+
amb
25/33
amb