VNQ600TR-E STMicroelectronics, VNQ600TR-E Datasheet - Page 18
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VNQ600TR-E
Manufacturer Part Number
VNQ600TR-E
Description
IC SSR HIGH SIDE 4CH 25A 28SOIC
Manufacturer
STMicroelectronics
Type
High Sider
Datasheet
1.VNQ600.pdf
(26 pages)
Specifications of VNQ600TR-E
Input Type
Non-Inverting
Number Of Outputs
4
On-state Resistance
35 mOhm
Current - Output / Channel
15A
Current - Peak Output
40A
Voltage - Supply
5.5 V ~ 36 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Application information
3.1.2
3.2
3.3
18/26
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
R
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
Solution 2: a diode (D
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving
an inductive load. This small signal diode can be safely shared amongst several different
HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in
the input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift will not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
Load dump protection
D
V
line that are greater than those shown in the ISO T/R 7637/1 table.
MCU I/O protection
If a ground protection network is used and negative transients are present on the V
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
Example
For the following conditions:
Recommended values are:
CC
GND
ld
is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
maximum DC rating. The same applies if the device is subject to transients on the V
-V
V
I
V
5kΩ ≤ R
R
latchup
will produce a shift (I
OHµC
CCpeak
prot
CCpeak
=10kΩ
≥ 4.5V
≥ 20mA
prot
= - 100V
/I
latchup
≤ 65kΩ .
≤ R
prot
S(on)max
≤ (V
GND
OHµC
) in the ground line
* R
-V
GND
IH
GND
-V
.
GND
) in the input thresholds and the status output
) / I
IHmax
S(on)max
becomes the sum of the
prot
) in line to
VNQ600
CC
line,
CC