A4984SLPTR-T Allegro Microsystems Inc, A4984SLPTR-T Datasheet - Page 18

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A4984SLPTR-T

Manufacturer Part Number
A4984SLPTR-T
Description
IC STEPPER MOTOR DRIVER 24TSSOP
Manufacturer
Allegro Microsystems Inc
Datasheet

Specifications of A4984SLPTR-T

Applications
Stepper Motor Driver
Number Of Outputs
1
Current - Output
±2A
Voltage - Load
8 V ~ 35 V
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
Motor Type
Stepper
No. Of Outputs
2
Output Current
2A
Output Voltage
35V
Supply Voltage Range
3V To 5.5V
Driver Case Style
TSSOP
No. Of Pins
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
620-1377 - Board Eval Motor Control A4984
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
620-1341-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A4984SLPTR-T
Manufacturer:
POWEREX
Quantity:
100
Part Number:
A4984SLPTR-T
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
A4984
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
ENABLE
OUT2B
GND
Terminal List Table
VCP
CP1
CP2
SENSE1
SENSE2
¯ E ¯ ¯ N ¯ ¯ A ¯ ¯ B ¯ ¯ L ¯ ¯ E ¯
OUT1A
OUT1B
OUT2A
OUT2B
¯ S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯
¯ R ¯ ¯ E ¯ ¯ S ¯ ¯ E ¯ ¯ T ¯
ROSC
VREG
Name
STEP
VBB1
VBB2
GND
MS1
MS2
VCP
VDD
CP1
CP2
REF
PAD
DIR
NC
1
2
3
4
5
6
ES Package
PAD
3, 16
ES
17
21
18
22
15
10
11
20
23
12
14
19
24
13
4
5
2
8
9
1
6
7
18
17
16
15
14
13
OUT1B
DIR
GND
REF
STEP
VDD
26, 28, 29, 31
2, 4, 21, 23,
Number
DMOS Microstepping Driver with Translator
6, 19
ET*
20
12
27
24
30
18
13
14
25
32
15
17
22
16
10
11
7
8
5
1
3
9
ENABLE
OUT2B
VBB2
GND
CP1
CP2
NC
NC
13, 24
1
2
3
4
5
6
7
8
LP
Pin-out Diagrams
14
23
18
15
19
22
12
17
20
16
21
10
11
1
2
5
6
7
8
9
3
4
ET Package
Charge pump capacitor terminal
Charge pump capacitor terminal
Logic input
Logic input
Ground
Logic input
Logic input
No connection
DMOS Full Bridge 1 Output A
DMOS Full Bridge 1 Output B
DMOS Full Bridge 2 Output A
DMOS Full Bridge 2 Output B
G
Logic input
Timing set
Sense resistor terminal for Bridge 1
Sense resistor terminal for Bridge 2
Logic input
Logic input
Load supply
Load supply
Reservoir capacitor terminal
Logic supply
Regulator decoupling terminal
Exposed pad for enhanced thermal dissipation*
PAD
m
reference voltage input
24
23
22
21
20
19
18
17
And Overcurrent Protection
OUT1B
NC
VBB1
NC
DIR
GND
REF
STEP
Description
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
RESET
SLEEP
ROSC
VREG
STEP
VDD
VCP
MS1
MS2
REF
CP1
CP2
10
11
12
1
2
3
4
5
6
7
8
9
LP Package
PAD
24
23
22
21
20
19
18
17
16
15
14
13
GND
ENABLE
OUT2B
VBB2
SENSE2
OUT2A
OUT1A
SENSE1
VBB1
OUT1B
DIR
GND
18

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