A3932SEQ Allegro Microsystems Inc, A3932SEQ Datasheet - Page 8

• Manufacturer Part Number: A3932SEQ
• Description: IC CTRLR MOSFET 3PH 32-PLCC
• Manufacturer: Allegro Microsystems Inc

Specifications of A3932SEQ

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 18 V ~ 50 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Load: -

FAULT — Open-drain output to indicate fault condition; FAULT
= 1 (external pull-up) for any of the following:
1 – invalid HALL input code,
2 – undervoltage condition detected at VREG.
3 – thermal shutdown, or
4 – motor lead (SA/SB/SC) shorted to ground.
high-side drivers, faults will force a coast condition that turns off
all power MOSFETs. Only the short-to-ground fault is latched
but is cleared at each com mu ta tion. If the motor has stalled
due to a short-to-ground being detected, toggling the RESET
ter mi nal or repeating a power-up sequence will clear the fault.
Typically pulled up to V
resistor.
MODE — A logic input to set current-decay method, internally
pulled up to V
= 1), only the high-side MOSFET is switched off during a
PWM-off cycle. The fast-decay mode (MODE = 0) switches
both the high-side and low-side MOSFETs.
H1/H2/H3 — Hall-sensor inputs; internally pulled up to V
(+5 V). Con fi g ured for 120° electrical spacing.
DIR — A logic input to reverse rotation, see Commutation Truth
Table. Internally pulled up to V
BRAKE — An active-low logic input for a braking function.
A BRAKE = 0 will turn on the low-side FETs and turn off the
high-side FETs. This will effectively short-circuit the BEMF in
the wind ings and brake the motor. The braking torque applied
will depend on the speed. Internally pulled up to V
RESET = 1 overrides BRAKE and will coast the motor.
SR — Synchronous rectifi cation input. An SR = 0 disables this
feature, forcing current decay through the body diodes of the
power MOSFETs. An SR = 1 will result in ap pro pri ate high-
and low-side gate outputs to switch in re sponse to a PWM-off
com mand. Internally pulled up to V
Input Logic table.
TACH — An open-drain digital output whose frequency is pro-
portional to speed of rotation. A pulse appears at every HALL
transition. Typ i cal ly pulled up to V
5.1 kΩ resistor.
A3932
Except for a short-to-ground fault that only turns off the
LCAP
(+5 V). When in slow-decay mode (MODE
LCAP
(+5 V) with an external 5.1 kΩ
LCAP
LCAP
LCAP
(+5 V).
(+5 V) with an external
(+5 V). See also the
Terminal Descriptions (cont’d)
LCAP
Three-Phase Power MOSFET Controller
(+5 V).
LCAP
PWM — Speed control input, internally pulled up to V
(+5 V). A PWM = 0 turns off selected drivers. A PWM = 1 will
turn on selected drivers as determined by H1/H2/H3 input logic.
Hold ing PWM = 1 allows speed/torque control solely by the
internal current-limit circuit with the REF analog voltage. See
also the Input Logic table
RC — An analog input used to set the fi xed off time with an
external resistor (R
trolled by the value of the external ca pac i tor (see Ap pli ca tions
Information). See Application Information.
SENSE — An analog input to the current-lim it com par a tor.
A voltage rep re sent ing load current appears on this ter mi nal dur-
ing on time, when it reaches REF voltage, the comparator trips
and load current decays for the fi xed off-time interval. Volt-
age transients seen at this ter mi nal when the drivers turn on are
ignored for time t
REF — An analog input to the current-lim it com par a tor. Volt-
age applied here with respect to AGND sets the peak load cur-
rent.
VREG — A regulated 13 V output; supply for low-side gate
drive and boot strap capacitor charge circuits. It is good practice
to connect a decoupling capacitor from this ter mi nal to AGND,
as close to the de vice ter mi nals as pos si ble. This terminal should
be shorted to V
VBB — The A3932 supply voltage. It is good practice to con-
nect a decoupling capacitor from this ter mi nal to AGND, as
close to the de vice ter mi nals as pos si ble.
LCAP — Con nec tion for 0.1 μF decoupling capacitor for the
internal 5 V reference. This terminal can source no more than
3 mA for the DEAD input, TACH and FAULT outputs.
DEAD — An analog input. A resistor between DEAD and
LCAP is selected to adjust the turn-off to turn-on time. This
delay is needed to prevent shoot-through in the external power
MOSFETs. See Applications Information for details on setting
dead time.
AGND — The low-level (analog) reference point.
PGND — The return for all low-side gate drivers.
be connected to the system power ground.
BB
blank
for 12 V applications.
T
) and capacitor (C
.
I
peak
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
= V
REF
/R
T
S
). The t
.
.
blank
time is con-
This should
LCAP
8