A3958SLB Allegro Microsystems Inc, A3958SLB Datasheet - Page 7

• Manufacturer Part Number: A3958SLB
• Description: IC MOTOR DRIVER PWM FULL 24-SOIC
• Manufacturer: Allegro Microsystems Inc

Specifications of A3958SLB

• Applications: PWM Motor Driver
• Number Of Outputs: 1
• Current - Output: ±2A
• Voltage - Load: 20 V ~ 50 V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

D15 Phase Logic. Bit D15, in conjunction with PHASE,
determines if the device is operating in the forward
(PHASE ≠ D15) or reverse (PHASE = D15) state.
D16 G
RANGE, determines if V
D16) or by 10 (RANGE = D16).
D17 Internal PWM Mode. Bit D17, in conjunction with
MODE, selects slow (MODE ≠ D17) or mixed (MODE =
D17) current decay.
A3958
PHASE D15 State
m
STROBE
MODE D17
Range Select. Bit D16, in conjunction with
CLOCK
0
1
0
1
DATA
0
1
0
1
RANGE
0
1
0
1
0
0
1
1
0
0
1
1
Reverse
Forward
Forward
Reverse
REF
Current-Decay Mode
D16
C
is divided by 5 (RANGE ≠
0
0
1
1
A
D19
Mixed
Mixed
Slow
Slow
FUNCTIONAL DESCRIPTION (continued)
Divider
OUT
High
High
Low
Low
÷10
÷10
B
÷5
÷5
A
D
OUT
High
High
Low
Low
Serial Port Write Timing
DMOS Full-Bridge PWM Motor Driver
B
E
D18 Test Mode. Bit D18 low (default) operates the
device in normal mode. D18 is only used for testing
purposes. The user should never change this bit.
D19 Sleep Mode. Bit D19 selects a Sleep mode to
minimize power consumption when not in use. This
disables much of the internal circuitry including the
regulator and charge pump. On power up the serial port is
initialized to all 0s. Bit D19 should be programmed high
for 1 ms before attempting to enable any output driver.
Serial Port Write Timing Operation. Data is clocked
into the shift register on the rising edge of the CLOCK
signal. Normally STROBE will be held high, only brought
low to initiate a write cycle. Refer to diagram below and
these specifi cations for the minimum timing requirements.
V
the sink-side DMOS outputs. The V
be decoupled with a 0.22 μF capacitor to ground. V
D18
REG
A. DATA setup time ........................................... 15 ns
B. DATA hold time ............................................ 10 ns
C. Setup STROBE to CLOCK rising edge ........ 50 ns
D. CLOCK high pulse width ............................. 50 ns
E. CLOCK low pulse width ............................... 50 ns
F. Setup CLOCK rising edge to STROBE ........ 50 ns
G. STROBE pulse width ................................... 50 ns
. This internally generated voltage is used to operate
D19
0
1
D0
Sleep Mode
Sleep
Normal
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
F
REG
terminal should
G
Dwg. WP-038
REG
is
6