A3946KLP-T Allegro Microsystems Inc, A3946KLP-T Datasheet - Page 12

• Manufacturer Part Number: A3946KLP-T
• Description: IC MOSFET CONTROLLER 16-TSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A3946KLP-T

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 7 V ~ 60 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Load: -
• Other names: 620-1061

A3946
Terminal List Table
The PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
~FAULT
Name
PGND*
RESET
LGND*
VREG
BOOT
VREF
VBB
PAD
CP2
CP1
IN1
IN2
GH
GL
DT
S
Number
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
–
Gate drive supply.
Charge pump capacitor, positive side. When not using the charge pump, leave this pin open.
Charge pump capacitor, negative side. When not using the charge pump, leave this pin open.
External ground. Internally connected to the power ground.
Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control
slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap
capacitor and negative supply connection for the fl oating high-side drive.
High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to
control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
High-side connection for bootstrap capacitor, positive supply for the high-side gate drive.
Diagnostic output, open drain. Low during a fault condition.
Logic control.
Logic control.
Logic control input. When RESET = 0, the chip is in a very low power sleep mode.
External ground. Internally connected to the logic ground.
Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this
input high disables the dead time circuit and changes the logic truth table.
5 V internal reference decoupling terminal.
Supply Input.
Exposed thermal pad. Not connected to any pin, but should be externally connected to ground, to reduce
noise pickup by the pad.
PGND
VREG
BOOT
CP2
CP1
GH
GL
S
Pin-out Diagram
1
2
3
4
5
6
7
8
LP package
PAD
Half-Bridge Power MOSFET Controller
16
15
14
13
12
11
10
9
Description
VBB
VREF
DT
LGND
RESET
IN2
IN1
~FAULT
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
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