LP3906SQ-DJXI/NOPB National Semiconductor, LP3906SQ-DJXI/NOPB Datasheet - Page 32

• Manufacturer Part Number: LP3906SQ-DJXI/NOPB
• Description: IC REG DC-DC/LINEAR DUAL 24-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3906SQ-DJXI/NOPB

• Applications: Digital Cores
• Current - Supply: 60µA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LLP
• For Use With: LP3906SQ-JXXIEV - BOARD EVALUATION LP3906SQ-JXXI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LP3906SQ-DJXI; LP3906SQ-DJXITR

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Application Notes
SYSTEM CLOCK INPUT (SYNC) PIN
Pin 23 of the chip allows for a system clock input in order to
synchronize the buck converters in PWM mode. This is useful
if the user wishes to force the bucks to work synchronously
with the system. Otherwise, the user should tie the pin to GND
and the bucks will operate on an internal 2 MHz clock.
The signal applied to the SYNC pin must be 13 MHz as per
application processor specifications, but we can be contacted
to modify that specification if so desired. Upon inputting the
13 MHz clock signal, the bucks will scale it down and continue
to run at 2 MHz based off the 13 MHz clock.
ANALOG POWER SIGNAL ROUTING
All power inputs should be tied to the main VDD source (i.e.
battery), unless the user wishes to power it from another
source. (i.e. external LDO output).
The analog VDD inputs power the internal bias and error am-
plifiers, so they should be tied to the main VDD. The analog
VDD inputs must have an input voltage between 2.7 and 5.5
V, as specified on pg. 6 of the datasheet.
The other V
have inputs lower than 2.7V, as long as it's higher than the
programmed output (+0.3V, to be safe).
The analog and digital grounds should be tied together out-
side of the chip to reduce noise coupling.
COMPONENT SELECTION
Inductors for SW1 and SW2
There are two main considerations when choosing an induc-
tor; the inductor should not saturate and the inductor current
ripple is small enough to achieve the desired output voltage
ripple. Care should be taken when reviewing the different sat-
uration current ratings that are specified by different manu-
facturers. Saturation current ratings are typically specified at
25ºC, so ratings at maximum ambient temperature of the ap-
plication should be requested from the manufacturer.
There are two methods to choose the inductor saturation cur-
rent rating:
Method 1
The saturation current is greater than the sum of the maxi-
mum load current and the worst case average to peak induc-
tor current. This can be written as follows:
I
I
V
L:
f:
V
RIPPLE
OUTMAX
IN
OUT
:
:
:
: Maximum load current
Average to peak inductor current
Maximum input voltage to the buck
Min inductor value including worse case tolerances
(30% drop can be considered for method 1)
Minimum switching frequency (1.6 MHz)
Buck Output voltage
IN
s (V
IN
LDO1, V
IN
LDO2, V
IN
1, V
IN
2) can actually
32
Method 2
A more conservative and recommended approach is to
choose an inductor that has saturation current rating greater
than the maximum current limit of 2375 mA.
Given a peak-to-peak current ripple (I
to be at least
External Capacitors
The regulators on the LP3906 require external capacitors for
regulator stability. These are specifically designed for
portable applications requiring minimum board space and
smallest components. These capacitors must be correctly se-
lected for good performance.
LDO CAPACITOR SELECTION
Input Capacitor
An input capacitor is required for stability. It is recommended
that a 1.0 μF capacitor be connected between the LDO input
pin and ground (this capacitance value may be increased
without limit).
This capacitor must be located a distance of not more than 1
cm from the input pin and returned to a clean analog ground.
Any good quality ceramic, tantalum, or film capacitor may be
used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge currents when connected to a low
impedance source of power (like a battery or a very large ca-
pacitor). If a tantalum capacitor is used at the input, it must be
guaranteed by the manufacturer to have a surge current rat-
ing sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and tem-
perature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain approximately
1.0 μF over the entire operating temperature range.
Output Capacitor
The LDOs on the LP3906 are designed specifically to work
with very small ceramic output capacitors. A 1.0 µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR be-
tween 5 mΩ to 500 mΩ, are suitable in the application circuit.
It is also possible to use tantalum or film capacitors at the
device output, C
for reasons of size and cost.
The output capacitor must meet the requirement for the min-
imum value of capacitance and also have an ESR value that
is within the range 5 mΩ to 500 mΩ for stability.
Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 0.47 µF to 4.7 µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 1.0 µF ceramic
capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability for the LDOs.
Inductor
L
SW
1,2
Value Unit Description
2.2
OUT
(or V
µH SW1,2 inductor
OUT
), but these are not as attractive
PP
) the inductor needs
Notes
D.C.R. 70 mΩ