MAX8664BEEP+ Maxim Integrated Products, MAX8664BEEP+ Datasheet - Page 22

• Manufacturer Part Number: MAX8664BEEP+
• Description: IC CNTRLR DUAL OUT 20-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX8664BEEP+

• Applications: Power Supplies
• Current - Supply: 1.4mA
• Voltage - Supply: 4.5 V ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To set the no-load output voltage (V
value of R3 as follows:
where V
when using the internal reference or V
nal reference). If the desired output voltage is equal to
the reference voltage (typical for tracking applications),
R3 is not installed.
To achieve the lowest possible load regulation in appli-
cations where voltage positioning is not desired, R1 is
not installed and R3 is calculated as follows:
To ensure stable operation, connect a compensation
capacitor (Cr) across the upper feedback resistor as
shown in Figure 7. To find the value of this capacitor,
follow the compensation design procedure below.
Choose a closed-loop bandwidth (f
1/3 the switching frequency (f
double pole (f
The FB peak-to-peak voltage ripple is:
The output ripple voltage due to the ESR of the output
capacitor, C
Target the feedback ripple in the 25mV to 60mV range.
For high duty-cycle applications (> 70%), a feedback
ripple of 25mV is recommended.
Low-Cost, Dual-Output, Step-Down
Controller with Fast Transient Response
22
V
______________________________________________________________________________________
FB RIPPLE
_
FB
V
OUT RIPPLE
f
O
is the feedback regulation voltage (0.6V
OUT,
R
O
=
3
) as follows:
_
2π
=
=
R
⎛
⎜
⎜
⎜
⎝
is:
3
⎛
⎜
⎝
1
=
V
L C
+
OUT
1
⎛
⎜
⎝
×
R
R
+
V
2
3
V
OUT
=
R
R
FB
OUT
+
⎛
⎜
⎝
−
2
1
V
V
ESR
R
R
V
V
OUT
FB
2
1
IN
FB
−
×
⎞
⎟
⎟
⎟
⎠
1
V
+
R
FB
S
⎞
⎟
⎠
R
×
(
L f
⎛
⎜
⎝
). Calculate the output
LOAD
LOAD
V
⎛
⎜
⎜
⎜
⎜
⎝
8
R
R
IN
×
⎞
⎟ ×
⎠
⎛
⎜
⎝
×
1
1
1
C
S
C
−
+
OUT
×
+
R
Compensation
1
O
) that is less than
V
R
2
+
+
OUT
REFIN2
DCR
R
R
LOAD
×
DCR
V
ESR
), calculate the
2
2
OUT
f
S
⎞
⎟
⎠
)
⎞
⎟
⎠
×
⎞
⎟ ×
⎠
for exter-
f
f
C
O
⎞
⎟
⎟
⎟
⎟
⎠
Finally, calculate the value of Cr as follows:
Each output of the MAX8664 is capable of driving two to
four external, logic-level, n-channel MOSFETs as the cir-
cuit switch elements. The key selection parameters are:
•
•
•
For a 5V input application, choose MOSFETs with rated
R
internal VL regulator provides 6.5V for gate drive in
order to minimize the on-resistance for a wide range of
MOSFETs.
For a good compromise between efficiency and cost,
choose the high-side MOSFETs that have conduction
losses equal to switching losses at nominal input voltage
and output current. Low R
side MOSFETs. Make sure that the low-side MOSFET(s)
does not spuriously turn on due to dV/dt caused by the
high-side MOSFET(s) turning on, as this would result in
shoot-through current and degrade the efficiency.
MOSFETs with a lower Q
immunity to dV/dt. For high-current applications, it is
often preferable to parallel two MOSFETs rather than to
use a single large MOSFET.
For proper thermal management, the power dissipation
must be calculated at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the-low side MOSFET(s),
the worst-case power dissipation occurs at the highest
duty cycle (V
as zero voltage switches; therefore, major losses are
the channel conduction loss (P
diode conduction loss (P
Use R
where V
dead time between high-side and low-side switching tran-
sitions (25ns typical), and f
DS(ON)
P
LSCC MAX
On-resistance (R
Maximum Drain-to-Source Voltage (V
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
Gate charges (Q
DS(ON)
Cr
P
F
(
LSDC(MAX)
at V
is the body diode forward-voltage drop, t
=
R
1
)
GS
IN(MAX)
at T
× ×
=
f
S
⎛
⎜
⎝
≤ 4.5V. With higher input voltages, the
1
J(MAX)
−
|
= 2 x I
(
V
g
V
). The low-side MOSFET(s) operate
DS(ON)
V
, Q
IN MAX
FB RIPPLE
V
OUT
V
OUT
(
IN
:
_
gd
LSDC
S
LOAD(MAX)
, Q
is the switching frequency.
(
gd
DS(ON)
)—the lower, the better.
V
)
IN
⎞
⎟ ×
⎠
gs
):
/ Q
−
)— the lower, the better.
MOSFET Selection
I
−
2
V
LOAD MAX
V
LSCC
OUT
gs
OUT RIPPLE
is preferred for low-
V
ratio have higher
(
F
)
_
) and the body
x t
DSS
DT
)
×
x f
R
)—should
)
DS ON
DT
S
|
(
is the
)