LTC3566EUF#TRPBF Linear Technology, LTC3566EUF#TRPBF Datasheet - Page 24

• Manufacturer Part Number: LTC3566EUF#TRPBF
• Description: IC USB POWER MANAGER 24-QFN
• Manufacturer: Linear Technology

Specifications of LTC3566EUF#TRPBF

• Applications: Handheld/Mobile Devices
• Voltage - Supply: 4.35 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

APPLICATIONS INFORMATION
smaller 0805 case. The size of the input overshoot will be
determined by the Q of the resonant tank circuit formed
by C
to measure the input ringing with the selected compo-
nents to verify compliance with the Absolute Maximum
specifi cations.
Alternatively, the following soft connect circuit (Figure 5)
can be employed. In this circuit, capacitor C1 holds MP1
off when the cable is fi rst connected. Eventually C1 begins
to charge up to the USB input voltage applying increasing
gate support to MP1. The long time constant of R1 and
C1 prevent the current from building up in the cable too
fast thus dampening out any resonant overshoot.
Buck-Boost Regulator Output Voltage Programming
The buck-boost regulator can be programmed for output
voltages greater than 2.75V and less than 5.5V. The output
voltage is programmed using a resistor divider from the
V
where V
Closing the Feedback Loop
The LTC3566 family incorporates voltage mode PWM
control. The control to output gain varies with operation
region (buck, boost, buck-boost), but is usually no greater
than 20. The output fi lter exhibits a double pole response
given by:
LTC3566/LTC3566-2
24
OUT1
V
f
FILTER _ POLE
IN
OUT1
5V USB
INPUT
pin connected to the FB1 pin such that:
and the input lead inductance. It is recommended
FB1
= V
USB CABLE
is fi xed at 0.8V (see Figure 6).
FB1
Figure 5. USB Soft Connect Circuit
=
R
R1
FB
2 • π • L • C
+1
C1
100nF
1
Si2333
MP1
OUT
R1
40k
Hz
C2
10μF
V
GND
LTC3566-2
LTC3566/
BUS
3566 F05
Where C
The output fi lter zero is given by:
where R
tance.
A troublesome feature in boost mode is the right-half plane
zero (RHP), and is given by:
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network (as shown in
Figure 6), can be incorporated to stabilize the loop but
at the cost of reduced bandwidth and slower transient
response. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
The unity-gain frequency of the error amplifi er with the
Type I compensation is given by:
Most applications demand an improved transient response
to allow a smaller output fi lter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
Type III compensation also reduces any V
seen at start-up.
The compensation network depicted in Figure 7 yields the
transfer function:
f
f
f
(
s • 1+
V
1+ sR2C2
FILTER _ ZERO
RHPZ
UG
V
OUT1
C1
=
OUT
ESR
=
2 • π • R1• C
=
sR2C1C2
2 • π •I
C1+C2
R1• C1+C2
is the output fi lter capacitor.
is the capacitor equivalent series resis-
)
• 1+ s(R1+R3)C3
(
1
(
=
1
OUT
2 • π • R
V
IN1
• 1+ sR3C3
P1
•L • V
(
2
)
Hz
•
ESR
OUT1
1
• C
Hz
)
)
OUT
Hz
OUT1
overshoot
3566fb