MAX8661ETL+T Maxim Integrated Products, MAX8661ETL+T Datasheet - Page 20

• Manufacturer Part Number: MAX8661ETL+T
• Description: IC POWER MANAGE XSCALE 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8661ETL+T

• Applications: Processor
• Voltage - Supply: 2.6 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Efficiency, Low-I
Voltage Management for Mobile Applications
20
MAX8660 MAX8661
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
______________________________________________________________________________________
PIN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NAME
AGND
RAMP
EN34
RSO
PG2
LBR
EN5
PG3
LBF
LX3
PV3
IN8
MR
V8
V3
IN
RE G 2 P ow er G r ound . C onnect P G 1, P G 2, P G 3, P G 4, and AG N D tog ether . Refer to the M AX 8660 E V
ki t data sheet for more information.
REG8 Input Power Connection. IN8 must be connected to IN.
Main Battery Input. This input provides power to the IC. Connect a 0.47µF ceramic capacitor from
IN to AGND.
Analog Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit
data sheet for more information.
REG8 Always-On 3.3V LDO Output. REG8 is the first regulator that powers up in the
MAX8660/MAX8661. REG8 is supplied from IN and supplies up to 30mA. V8 is internally pulled to
AGND through 1.5kΩ during IN undervoltage or overvoltage lockout. Connect V8 to VCC_BBATT
on Marvell PXA3xx processors.
Low-Battery Detect Falling Input. The LBF threshold is 1.20V. Connect LBF to LBR for 50mV
hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBF sets the falling voltage at
which LBO goes low. See the Low-Battery Detector ( LBO , LBF, LBR) section for more information.
Low-Battery Detect Rising Input. The LBR threshold is 1.25V. Connect LBF to LBR for 50mV
hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBR sets the rising voltage at
which LBO goes high. See the Low-Battery Detector ( LBO , LBF, LBR) section for more
information.
Manual Reset Input. A low MR input causes RSO to go low and resets all serial programmed
registers to their default values. See the Reset Output ( RSO ) and MR Input section for more
information.
Ramp-Rate Input. Connect a resistor from RAMP to AGND to set the regulator ramp rates. See the
Ramp-Rate Control (RAMP) section for more information.
REG5 Enable Input. Drive EN5 high to turn on REG5. EN5 has hysteresis so an RC can be used to
implement manual sequencing with respect to other inputs. EN5 is typically driven by the SYS_EN
output of an Marvell PXA3xx processor.
RE G 3 P ow er G r ound . C onnect P G 1, P G 2, P G 3, P G 4, and AG N D tog ether . Refer to the M AX 8660 E V
ki t data sheet for more information.
REG3 Switching Node. Connect LX3 to the REG3 inductor. LX3 is high impedance when REG3 is
shut down.
REG3 Power Input. Connect a 4.7µF ceramic capacitor from PV3 to PG3. All PV pins and IN must
be connected together externally.
Open-Drain Reset Output. RSO typically connects to the nRESET input on an applications
processor. An output low from the MAX8660/MAX8661 RSO resets all serial programmed
registers to their default values and causes the processor to enter its reset state. See the Reset
Output ( RSO ) and MR Input section for more information.
REG3 Voltage Sense Input. Connect V3 directly to the REG3 output voltage. The output voltage i s
ad j ustab l e fr om 0.725V to 1.8V thr oug h the ser i al i nter face. V 3 i s i nter nal l y p ul l ed to AGN D thr oug h
550Ω w hen RE G3 i s shut d ow n. V 3 connects to V C C _AP P S on M ar vel l P X A3xx p r ocessor s.
REG3 and REG4 Active-High Hardware Enable Input. Drive EN34 high to enable both REG3 and
REG4. Drive EN34 low to allow the serial interface to enable REG3 and REG4 independently.
EN34 has hysteresis so an RC can be used to implement manual sequencing with respect to
other inputs. EN34 is typically driven by the PWR_EN output of an Marvell PXA3xx processor. See
the REG3/REG4 Enable (EN34, EN3, EN4) section for more information.
Q
, PMICs with Dynamic
FUNCTION
Pin Description (continued)