MAX8660ETL+ Maxim Integrated Products, MAX8660ETL+ Datasheet - Page 30

• Manufacturer Part Number: MAX8660ETL+
• Description: IC POWER MANAGE XSCALE 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Low-IQ PMICr

Specifications of MAX8660ETL+

• Applications: Processor
• Voltage - Supply: 2.6 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Output Voltage Range: 1.764 V to 1.836 V
• Input Voltage Range: 2.6 V to 6 V
• Input Current: 20 uA
• Power Dissipation: 2857 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 6V
• No. Of Outputs: 2
• Power Dissipation Pd: 2.857W
• Supply Voltage Range: 2.6V To 6V
• No. Of Pins: 40
• Filter Terminals: SMD
• Supply Voltage Min: 2.6V
• Rohs Compliant: Yes
• Frequency: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Efficiency, Low-I
Voltage Management for Mobile Applications
REG3 and REG4 have independent I
(EN3, EN4) and a shared hardware-enable input
(EN34). As shown in Figure 5, the EN34 hardware-
enable input is logically ORed with the I
Table 6 is the truth table for the V3/V4 enable logic.
Note that to achieve a pure I
EN34 to ground. Similarly, to achieve a pure hardware
enable/disable, leave the I
value (EN3 = EN4 = 0 = off); V3 and V4 cannot be inde-
pendently enabled/disabled using only hardware.
Note: A low MR drives RSO low and returns the I
registers to their default values: EN3 = 0 and EN4 = 0.
Table 6. Truth Table for V3/V4 Enable Logic
30
X = Don’t care.
HARDWARE INPUT
EN34
Figure 5. V3/V4 Enable Logic
SDA
SCL
______________________________________________________________________________________
EN34
X
0
0
0
1
I
EN3
EN4
2
C
REG3/REG4 Enable (EN34, EN3, EN4)
ON
ON
REG4
REG3
0 (default)
EN3
X
0
1
1
2
C enable bits at their default
I
2
2
C enable/disable, connect
C BITS
PV3
LX3
PG3
PV4
LX4
PG4
0 (default)
EN4
X
1
0
1
2
2
C enable bits
C enable bits.
OFF
OFF
ON
ON
ON
V3
BATT
V4
(VCC_SRAM)
V3
(VCC_APPS)
BATT
Q
OFF
OFF
ON
ON
ON
V4
, PMICs with Dynamic
2
C
The MAX8660/MAX8661 provide numerous enable sig-
nals (Table 5) and support any combination for enabling
and disabling their supplies with these signals. Table 7
shows several power modes defined for PXA3xx
processors along with their corresponding MAX8660/
MAX8661 quiescent operating currents.
Figure 6 shows the power-up sequence for the Marvell
PXA3xx family of processors. In general, the supplies
should power up in the following order:
1) POWER-UP: V8 ➔ V5 ➔ V1 and V2 ➔ V3 and V4
2) REG6 and REG7 typically power external card slots
Note that the Marvell PXA3xx processor controls
EN1/EN2/EN5 with the same SYS_EN signal, yet Marvell’s
timing diagrams show that V5 is supposed to power up
before V1 and V2. Because of the PXA3xx family’s timing
parameters, most systems connect EN1/EN2/EN5
together and drive them with SYS_EN . When powering
up, this connection ensures that V5 powers up before
V1 and V2 (only when V5 is powered from IN).
The MAX8660/MAX8661 comply with the Marvell
PXA3xx power I
the PMIC to be used along with the processor with little-
to-no software development. As shown in Table 9, there
are many I
matically updates the PMIC through its power I
face, only the REG6 and REG7 enable bits need be
programmed to fully utilize the PMIC.
The Marvell PXA3xx processor contains a power man-
agement unit general configuration register (PCFR).
The default values of this register are compliant with the
MAX8660/MAX8661. However, wake-up performance
can be optimized using this register:
• The PCFR register contains timers for the SYS_DEL
• Enabling the “shorten wake-up delay” function
and PWR_DEL timing parameters as shown in Figure
6. Each timer defaults to 125ms. When using the
MAX8660/MAX8661, these timers may be shortened to
2ms to speed up the overall system wake-up delay.
(SWDD bit) bypasses the SYS_DEL and PWR_DEL
timers and uses voltage detectors on the Marvell
PXA3xx processor to optimize the overall system
wake-up delay.
and can be powered up and down based on appli-
cation requirements.
2
C registers, but since the processor auto-
2
C register specifications. This allows
Power-Up and Power-Down Timing
Configuration Register (PCFR)
Marvell PXA3xx Power
Power Modes
2
C inter-