U6808B-MFP Atmel, U6808B-MFP Datasheet - Page 4

• Manufacturer Part Number: U6808B-MFP
• Description: IC FAILSAFE W/RELAY DRVR 8-SOIC
• Manufacturer: Atmel

Specifications of U6808B-MFP

• Applications: Automotive
• Current - Supply: 15mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WDI Input
RCOSC Input
OSCERR Input
RESET Input
WD-OK Output
Watchdog State Diagram
4
U6808B
The microcontroller has to provide a trigger signal with the frequency f
the WDI input. A positive edge of f
counter and clocks the up/down counter additionally. The latter one counts only from
0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong
trigger decrements it by 1. As soon as the counter reaches status 3 the RS flip-flop is set
(see Figure 4). A missing incoming trigger signal is detected after 250 clocks of the inter-
nal watchdog frequency f
counter directly.
With an external R/C circuitry the IC generates a time base (frequency f
dent from the microcontroller. The watchdog's time window refers to a frequency of
f
A smart watchdog has to ensure that internal problems with its own time base are
detected and do not lead to an undesired status of the complete system. If the RC oscil-
lator stops oscillating a signal is fed to the OSCERR input after a timeout delay. It resets
the up/down counter and disables the WD-OK output.
Without this reset function the watchdog would freeze in its current status when f
stops.
During power-on and under/overvoltage detection a reset signal is fed to this pin. It
resets the watchdog timer and sets the initial state.
After the up/down counter is incremented to status 3 (see Figure 4) the RS flip-flop is set
and the WD-OK output becomes logic 1. This information is available for the microcon-
troller at the open-collector output ENABLE. If on the other hand the up/down counter is
decremented to 0 the RS flip-flop is reset, the WD-OK output and the ENABLE output
are disabled. The WD-OK output also controls a dual MUX stage which shifts the time
window by one clock after a successful trigger, thus forming a hysteresis to provide sta-
ble conditions for the evaluation of the trigger signal good or false. The WD-OK signal is
also reset in case the watchdog counter is not reset after 250 clocks (missing trigger
signal).
Figure 4. Watchdog State Diagram
WDC
= 100 ´ f
WDI
bad
Initial status
good
O/F
RC
(see section “WD-OK Output”) and resets the up/down
bad
bad
1/NF
1/F
WDI
detected by a slope detector resets the binary
good
good
bad
bad
2/NF
2/F
bad
good
good
3/NF
good
WDI
4707A–AUTO–05/03
which is fed to
WDC
) indepen-
RC