IR3505MPBF International Rectifier, IR3505MPBF Datasheet - Page 15

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IR3505MPBF

Manufacturer Part Number
IR3505MPBF
Description
IC XPHASE3 CONTROL 16-MLPQ
Manufacturer
International Rectifier
Series
XPhase3™r
Datasheet

Specifications of IR3505MPBF

Applications
Processor
Current - Supply
3mA
Voltage - Supply
8 V ~ 16 V
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-MLPQ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IR3505MPBF
Quantity:
9 000
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the
PCB layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND)
• Separate analog bus (EAIN, DACIN, and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to
• Connect PGND to LGND pins to their respective ground planes through vias.
• Place current sense resistors and capacitors (R
• Place the decoupling capacitor C
• Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET.
• There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor,
and power ground plane (PGND).
reduce the noise coupling.
the inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs
and bootstrap nodes.
inductance of the gate drive paths.
Use combination of different packages of ceramic capacitors.
output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and
the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for
connections between layers.
Page 15 of 19
PLANE
PLANE
PGND
PGND
To Bottom
To Bottom
MOSFET
MOSFET
To Gate
To Gate
Voltage
Voltage
Drive
Drive
C
VCCL
BST
D
To Digital Bus
To Digital Bus
PHSOUT
PHSOUT
VCCL
GATEL
GATEL
To Switching
To Switching
CLKIN
CLKIN
PGND
PGND
as close as possible to the VCCL pin.
C
BST
Node
Node
VCCL
PHSIN LGND DACIN
CS
BOOST
and C
GATEH
To Analog Bus
To Analog Bus
MOSFET
MOSFET
To Top
To Top
ISHARE
SW
CS
) close to phase IC. Use Kelvin connection for
CSIN -
CSIN+
CSIN -
VCC
VCC
EAIN
EAIN
To LGND
To LGND
Plane
Plane
R
C
VCC
To VIN
To VIN
To Inductor
To Inductor
C
CS
CS
Ground
Ground
Polygon
Polygon
PLANE
PLANE
LGND
LGND
Sept 26
th
IR3505
, 2007

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