IR3510MPBF International Rectifier, IR3510MPBF Datasheet - Page 25

• Manufacturer Part Number: IR3510MPBF
• Description: IC XPHASE CONTROL 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase™r

Specifications of IR3510MPBF

• Applications: Processor
• Mounting Type: Surface Mount
• Package / Case: 32-MLPQ
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -

Under Voltage Lock Out
There are two UVLOs, UVLO1 for Vcc and UVLO2 for P12V which is the voltage after the input FET. The UVLO1
for Vcc has the start threshold of 9V and stop threshold of 8.2V. It controls the Charge Pump, the enable of the
input FET, and the reset of the input fault latch. Any fault latch can be reset by cycling either Enable or Vcc.
The UVLO2 for P12V has the start threshold of 8.9V and the stop threshold of 8.1V. The UVLO2 threshold tracks
the UVLO1 threshold to make sure the input FET is turned on without larger voltage droop across the input FET.
The UVLO2 controls the input soft-start regulator, second soft-start cycle, and the turn-on of the voltage regulator
output.
Input FET Short Detection
Detecting a failed input FET is critical for hot-swap and OVP. But, it’s hard to detect when it is turned on, since its
failure mode is shorted. A logic circuit is added to detect the P12V voltage before enabling the input FET. If it’s
above the UVLO2 threshold before the input FET is turned on, it declares the input FET shorted and latches the
fault.
Over-Voltage Protection
The OVP comparator compares the voltage on the “OVPSET” pin and the voltage on the “OVPSNS” pin. The
“OVPSET” voltage from the system sets the threshold of the OVP. The “OVPSNS” voltage is directly from the
remote sense amplifier output “VO”, or through a resistor divider to match the “OVPSET” voltage.
Once the OV condition is detected, it turns on the “Body-Braking Disable” circuit first to turn on all the bottom FETs.
After 5uS delay, it turns off the input FET and latches the fault.
In a redundant system, the OV condition can be caused by any of the paralleled voltage regulators. In order to
isolate the bad module but still keep the system running, “ORING” signal is used to determine which module is
causing the OV, since only the bad module is having HIGH “ORING” signal. So, only the bad module will be
disabled and latched off. All the good modules will resume supplying the load once the bad module is isolated and
the OV condition is removed.
Fig. 14a shows the OVP response in a bad module, and Fig. 14b shows the OVP response in a good module.
12V IN
Enable
P12V
UVLO2
Vss
EAOUT
Vout
VRRDY
ORING
Iout
Page 25 of 36
Soft-Start
3.8V
VRM
1.3V
Fig. 14a Bad module OVP response
3.6V
Normal Operation
IR Confidential
UVLO2 Vth
OVP Vth
Bot FET On
OVP
VRM OVP Latch
Vset
Reset Fault Latch
May 18, 2009
IR3510