MAX1865TEEP+T Maxim Integrated Products, MAX1865TEEP+T Datasheet - Page 20

• Manufacturer Part Number: MAX1865TEEP+T
• Description: IC PWR SUPPLY CONTROLLER 20QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1865TEEP+T

• Applications: Power Supply Controller
• Voltage - Input: 4.5 ~ 28 V
• Current - Supply: 1.4mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies
The pass transistors must meet specifications for cur-
rent gain (h
uration voltage, and power dissipation. The transistor’s
current gain limits the guaranteed maximum output cur-
rent to:
where I
(220Ω) is the pullup resistor connected between the
transistor’s base and emitter. Furthermore, the transis-
tor’s current gain increases the linear regulator’s DC
loop gain (see Stability Requirements), so excessive
gain will destabilize the output. Therefore, transistors
with current gain over 100 at the maximum output cur-
rent, such as Darlington transistors, are not recom-
mended. The transistor’s input capacitance and input
resistance also create a second pole, which could be
low enough to destabilize the output when heavily
loaded.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator will support.
Alternatively, the package’s power dissipation could
limit the useable maximum input-to-output voltage dif-
ferential. The maximum power dissipation capability of
the transistor’s package and mounting must exceed the
actual power dissipation in the device. The power dissi-
pated equals the maximum load current times the maxi-
mum input-to-output voltage differential:
The MAX1864/MAX1865 linear regulators use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, pass
transistor’s specifications, the base-emitter resistor,
and the output capacitor determine the loop stability. If
the output capacitor and pass transistor are not proper-
ly selected, the linear regulator will be unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain
(A
20
V(LDO)
P I
______________________________________________________________________________________
=
LOAD MAX
DRV
I
) is approximately:
LOAD MAX
FE
is the minimum base-drive current, and R
(
), input capacitance, collector-emitter sat-
(
)
(
V
)
LDOIN
=
⎡
⎢
⎢
⎣
I
DRV
-
V
-
OUT
⎛
⎜
⎝
R
V
BE
BE
Stability Requirements
)
Transistor Selection
=
⎞
⎟
⎠
⎤
⎥
⎥
⎦
I
LOAD MAX CE
h
FE MIN
(
(
)
)
V
BE
where V
base-to-emitter resistor (R
ly 220Ω, providing approximately 3.2mA of bias current.
The output capacitor creates the dominant pole.
However, the pass transistor’s input capacitance creates
a second pole in the system. Additionally, the output
capacitor’s ESR generates a zero, which may be used to
cancel the second pole if necessary. Therefore, to
achieve stable operation, use the following equations to
verify that the linear regulator is properly compensated:
1) First, determine the dominant pole set by the linear
2) Next, determine the second pole set by the base-to-
3) A third pole is set by the linear regulator’s feedback
4) If the second and third poles occur well after unity-
However, if the ESR zero occurs before unity-gain
crossover, cancel the zero with ƒ
circuit components such that:
regulator’s output capacitor and the load resistor:
emitter capacitance (including the transistor’s input
capacitance), the transistor’s input resistance, and
the base-to-emitter pullup resistor:
resistance and the capacitance between FB_ and
GND, including 20pF stray capacitance:
gain crossover, the linear regulator will remain stable:
Unity Gain Crossover A
ƒ
POLE CLDO
ƒ
T
A
POLE CBE
ƒ
(
is 26mV, and I
V LDO
POLE CBE
(
ƒ
(
POLE FB
(
)
)
=
≈
)
2
⎛
⎜
⎝
=
(
)
=
π
5 5
V
> ƒ
C
.
T
R I
2
2
)
2
LDO LOAD
BE LOAD
π
⎞
⎟
⎠
π
=
=
BIAS
BE
C
POLE CLDO
C
⎡
⎢
⎢
⎣
1
1
2
BE
BE BE T FE
R
). This bias resistor is typical-
π
+
V LDO POLE CLDO
C
(
(
R
⎛
⎜
⎝
is the current through the
R
(
FB
I
BIAS FE
BE
I
+
LOAD
(
1
1
V h
R
POLE(FB)
)
V h
||
ƒ
1
=
T FE
h
R
||
)
2
IN NPN
A
R
I
π
LOAD MAX
V LDO
(
2
C
⎞
⎟
⎠
(
)
⎤
⎥
⎥
⎦
(
LDO LDO
V
by changing
REF
)
(
)
)
V
)
)