MAX6636UP9A+ Maxim Integrated Products, MAX6636UP9A+ Datasheet - Page 9

• Manufacturer Part Number: MAX6636UP9A+
• Description: IC PREC TEMP MONITOR 7CH 20TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX6636UP9A+

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Buffer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Full Temp Accuracy: - 0.1 C, 3 C
• Digital Output - Bus Interface: Serial (2-Wire)
• Digital Output - Number Of Bits: 11 bit
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are 11 alarm threshold registers that store over-
temperature ALERT and OVERT threshold values.
Seven of these registers are dedicated to store one
local alert temperature threshold limit and six remote
alert temperature threshold limits (see the ALERT
Interrupt Mode section). The remaining four registers
are dedicated to remote channels 1, 4, 5, and 6 to store
overtemperature threshold limits (see the OVERT
Overtemperature Alarms section). Access to these reg-
isters is provided through the SMBus interface.
Figure 3. SMBus Write-Timing Diagram
Figure 4. SMBus Read-Timing Diagram
SMBCLK
SMBDATA
SMBCLK
SMBDATA
A = START CONDITION.
B = MSB OF ADDRESS CLOCKED INTO SLAVE.
C = LSB OF ADDRESS CLOCKED INTO SLAVE.
D = R/W BIT CLOCKED INTO SLAVE.
E = SLAVE PULLS SMBDATA LINE LOW.
A = START CONDITION.
B = MSB OF ADDRESS CLOCKED INTO SLAVE.
C = LSB OF ADDRESS CLOCKED INTO SLAVE.
D = R/W BIT CLOCKED INTO SLAVE.
t
t
SU:STA
SU:STA
A
A
t
HD:STA
7-Channel Precision Temperature Monitor
t
HD:STA
_______________________________________________________________________________________
t
LOW
Alarm Threshold Registers
t
LOW
B
t
B
HIGH
t
HIGH
t
SU:DAT
t
SU:DAT
C
C
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER.
G = MSB OF DATA CLOCKED INTO MASTER.
H = LSB OF DATA CLOCKED INTO MASTER.
I = MASTER PULLS DATA LINE LOW.
E = SLAVE PULLS SMBDATA LINE LOW.
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER.
G = MSB OF DATA CLOCKED INTO SLAVE.
H = LSB OF DATA CLOCKED INTO SLAVE.
D
D
E
E
F
F
An ALERT interrupt occurs when the internal or external
temperature reading exceeds a high-temperature limit
(user programmable). The ALERT interrupt output sig-
nal can be cleared by reading the status register(s)
associated with the fault(s) or by successfully respond-
ing to an alert response address transmission by the
master. In both cases, the alert is cleared but is
reasserted at the end of the next conversion if the fault
condition still exists. The interrupt does not halt automat-
ic conversions. The ALERT output is open drain so that
multiple devices can share a common interrupt line. All
ALERT interrupts can be masked using the configuration
3 register. The POR state of these registers is shown in
Table 1.
t
HD:DAT
G
G
I = MASTER PULLS DATA LINE LOW.
J = ACKNOWLEDGE CLOCKED INTO SLAVE.
K = ACKNOWLEDGE CLOCK PULSE.
L = STOP CONDITION.
M = NEW START CONDITION.
H
H
J = ACKNOWLEDGE CLOCKED INTO SLAVE.
K = ACKNOWLEDGE CLOCK PULSE.
L = STOP CONDITION.
M = NEW START CONDITION.
ALERT Interrupt Mode
I
I
J
J K
K
t
SU:STO
t
SU:STO
L
L
t
BUF
t
BUF
M
M
9