MAX6660AEE+ Maxim Integrated Products, MAX6660AEE+ Datasheet - Page 16
![IC REG FAN SPEED 16-QSOP](/photos/6/61/66127/175-16-qsop_sml.jpg)
MAX6660AEE+
Manufacturer Part Number
MAX6660AEE+
Description
IC REG FAN SPEED 16-QSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX6660AEE.pdf
(21 pages)
Specifications of MAX6660AEE+
Function
Fan Control, Temp Monitor
Topology
ADC, Comparator, Fan Control, Multiplexer, Register Bank
Sensor Type
External
Sensing Temperature
External Sensor
Output Type
I²C™/SMBus™
Output Alarm
Yes
Output Fan
Yes
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Full Temp Accuracy
+/- 5 C
Digital Output - Bus Interface
Serial (2-Wire)
Digital Output - Number Of Bits
10 bit + Sign
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
range of reference clock full-scale frequencies from
33Hz to 66Hz. A further division is performed to set the
actual desired fan speed. This value appears in the Fan-
Speed Control register in thermal closed-loop mode. If
the thermal loop is open, but the fan-speed control loop
is closed, this value is programmable in the fan DAC.
When in fan open-loop mode (which forces the thermal
loop to open), the FSC register becomes a true DAC,
programming the voltage across the fan from zero to
nearly 12V to V
The tachometer input (TACH IN) includes a program-
mable (1/2/4/8) prescalar. The divider ratio for the
(1/2/4/8) prescalar is stored in the Fan Count Divisor
(FCD) register (Table 12). In general, the values in FC
Remote-Junction Temperature-Controlled
Fan-Speed Regulator with SMBus Interface
Table 10. Fan Gain Register (RFG/WFG)
Table 11. Fan Full-Scale Register (RFS/WFS)
Note: This register determines the maximum reference frequency at the input of the phase detector. It controls a programmable
16
Notes:
Bit 7:
Bits 6, 5: Fan gain of the fan loop, where 00 = 8°C with resolution = 4 bits. This means that the fan reaches its full-scale (maximum)
Bits 4, 3: Reserved.
Bit 2:
Bit 1:
Bit 0:
______________________________________________________________________________________
REGISTER/
COMMAND
ADDRESS
REGISTER/
POR State
COMMAND
divider that can be set anywhere between 127 and 255. The value in this register must be set in accordance with the proce-
dure described in the TACH IN section (equivalent to 8415/(Fan Frequency/Fan Count Divisor)). Programmed value below 127
defaults to 127. POR value is 255.
ADDRESS
POR State
Reserved. Always 1. If bit 7 is written to zero, then bits 7, 6, and 5 are set to 100.
speed when there is an 8°C difference between the remote-diode temperature and the value stored in TFAN
with a 5-bit resolution and 10 = 32°C with a 6-bit resolution.
SMBus Timeout. When 1, the SMBus timeout is disabled. This permits full I
to DC.
Fan feedback mode. When bit 1 is set to 1, the fan loop uses driver current sense rather than tachometer feedback.
Fan Driver Mode. When bit 0 is set to 1, the fan driver is in fan open-loop mode. In this mode, the fan DAC programs the
fan voltage rather than the fan speed. Tachometer feedback is ignored, and the user must consider minimum fan drive and
startup issues. Thermal open loop is automatically set to 1 (see Configuration register). Fan Fail (bit 0 of the Status register)
is set to 1 in this mode and should be ignored.
Bit
Bit
VFAN
.
Reserved
(MSB)
7
1
7
1
Data Bit
Fan Gain
6
1
6
0
READ/WRITE MAXIMUM TEMPERATURE LIMIT BYTE
Data Bit
Fan Gain
5
1
5
0
READ/WRITE FAN GAIN REGISTER
FS (1Fh = READ, 20h = WRITE)
FG (16h = READ, 1Bh = WRITE)
Data Bit
should be set such that the full-speed fan frequency
divided by the prescalar fall in the 33Hz to 66Hz range.
The (UP/DN) counter has six stages that form the input
of a 6-bit resistive ladder DAC whose voltage is divided
down from V
applied to the fan. Internal coding is structured such
that when in fan closed-loop mode (which includes
thermal closed loop) that higher values in the 0 to 32
range correspond to higher fan speeds and greater
voltage across the fan. In fan open-loop mode (which
forces thermal open loop) acceptable values range
from 0 to 63 (3Fh) for proportional control; a value of 64
(40h) commands unconditional full speed.
4
1
4
x
Data Bit
2
3
1
VFAN
C compatibility with minimum clock frequency
3
x
. This DAC determines the voltage
Data Bit
Timeout
SMBus
2
1
2
x
Feedback
Data Bit
Mode
Fan
1
1
1
0
,
01 = 16°C,
Data Bit
Driver
Mode
Fan
0
1
0
0