W83782G Nuvoton Technology Corporation of America, W83782G Datasheet
W83782G
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W83782G Summary of contents
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... W83782D/W83782G WINBOND H/W MONITORING Publication Release Date: April 14, 2005 Revision 2.0 ...
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... BEEP Control Register 2 − Index 57h (Bank 0)............................................................ 31 7.22 Chip ID − Index 58h (Bank 0) ....................................................................................... 32 7.23 Diode Selection Register − Index 59h (Bank 0)............................................................ 32 7.24 PWMOUT2 Control − Index 5Ah (Bank 0).................................................................... 33 7.25 PWMOUT1 Control − Index 5Bh (Bank 0).................................................................... 33 7.26 W83782D/W83782G - II - ...
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... Winbond Test Register − Index 50h (Bank 6)............................................................... 47 7.54 8. ELECTRICAL CHARACTERISTICS......................................................................................... 48 8.1 Absolute Maximum Ratings .......................................................................................... 48 8.2 DC Characteristics ........................................................................................................ 48 8.3 AC Characteristics ........................................................................................................ 50 9. HOW TO READ THE TOP MARKING...................................................................................... 53 10. PACKAGE DIMENTIONS ......................................................................................................... 54 11. APPLICATION CIRCUITS ........................................................................................................ 55 W83782D/W83782G Publication Release Date: April 14, 2005 - III - Revision 2.0 ...
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... PWM (pulse width modulation) outputs for fan speed control (3 are MUX optional) − Total sets of fan speed monitoring and controlling • Issue SMI#, OVT#, GPO# signals to activate system protection • Warning signal pop-up in application software W83782D/W83782G TM Deschutes CPU thermal diode output. Also the TM II) if applicable. This is Publication Release Date: April 14, 2005 ...
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... LQFP 3. KEY SPECIFICATIONS • Voltage monitoring accuracy • Monitoring Temperature Range and Accuracy − 40°C to +120°C • Supply Voltage • Operating Supply Current 5 mA typ. • ADC Resolution W83782D/W83782G interface ±1% (Max.) ± 3°C (Max Bits - support, for both ...
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... Output pin with 12 mA source-sink capability 12 AOUT - Output pin(Analog Open-drain output pin with 12 mA sink capability TTL level input pin TTL level input pin and schmitt trigger ts AIN - Input pin(Analog 3 W83782D Publication Release Date: April 14, 2005 - 3 - W83782D/W83782G VID2 PWMTOUT1 FAN1IO FAN2IO FAN3IO/PWMOUT2 VID4 CASEOPEN Revision 2.0 ...
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... I/O 12t Fan speed control PWM output +5V amplitude fan tachometer input / I/O Fan on-off control output. These multi-functional pins 12t can be programmable input or output. IN Serial Bus Clock Serial Bus bi-directional Data. 12 OUT Fan speed control PWM output W83782D/W83782G DESCRIPTION / / ...
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... This multi-functional pin is programmable. Thermistor 1 terminal input. (Default)/ AIN PentiumTM II diode 1 input. This multi-functional pin is programmable. Voltage Supply readouts from P6. This value is read in the IN t VID/Fan Divisor Register. OD Over temperature Shutdown Output W83782D/W83782G DESCRIPTION Publication Release Date: April 14, 2005 Revision 2.0 ...
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... ARDMSEL =0 or left open ) IN The hardware setting pin of 7 bit I t bit1 and bit0 at CR[48h]. (When ARDMSEL =1) Chip Select input from an external decoder which decodes IN high order address bits on the ISA Address Bus. This active low input W83782D/W83782G DESCRIPTION serial address bit2, ...
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... ISA Data Address Bus Bus Port 5h Index Register Port 6h Data Register Figure 1. ISA interface access diagram W83782D/W83782G Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h VID<3:0>/Fan Divisor Register 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto-increment) VID< ...
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... Serial Bus Address Byte Figure 3. Serial Bus Write to Internal Address Register Only R Ack by 781D Internal Index Register Byte 0 (Continued R Ack by 781D Internal Index Register Byte W83782D/W83782G Ack by Frame 2 781D Ack Stop by by 781D Master Frame 3 Data Byte Ack Stop by by Master ...
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... Internal Index Register Byte ... ... Ack Frame 2 by 782D MSB Data Byte R Ack by 782D ... ... Ack Frame 4 by 782D MSB Data Byte W83782D/W83782G Ack Stop by by Frame 2 Master Master , HYST ... ... Ack Ack by Frame 3 by Master Master LSB Data Byte , T OS HYST ...
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... R/W 0 Ack Frame 1 by 782D R Ack Frame 3 by 782D R Ack by 782D 0 SCL (Cont...) SDA (Cont...) Frame 3 Configuration Data Byte Figure 9. Configuration Register Write - 10 - W83782D/W83782G Ack Stop by by Master Master Frame 2 782D Pointer Byte Ack by Frame 4 Master MSB Data Byte Ack Frame 2 ...
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... D6 Ack by 781D +2.5VINA +2.5VINB Positive Inputs +3.3VIN VDD(+5V) VBAT R1 12VIN 10K, 1% VREF VTIN3 VTIN2 R THM VTIN1 10K **The Connections of VTIN1 and VTIN2 are same as VTIN3 Figure 11 W83782D/W83782G Ack Frame 2 by 782D Pointer Byte Ack by Frame 4 782D LSB Data Byte Pin 36 Pin 35 ...
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... R7=120K ohms and R8=56K ohms by the Winbond recommended. The expression equation of V6 With -5V voltage is shown as follows Ω ≅ Ω + Ω Ω 232 K + × Ω + 232 β − × VREF β − W83782D/W83782G + ) V 5 Ω ...
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... V6 can be evalated to be -5V. TM thermal diode or bipolar transistor 2N3904 TM R=30K, 1% C=3300pF R=30K C=3300pF D- Figure 12 W83782D/W83782G (Deschutes) thermal diode interface or VREF PIITDx W83782D PIITDx Publication Release Date: April 14, 2005 Revision 2 ...
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... Divisor TIME PER COUNTS REVOLUTION 6.82 ms 153 13.64 ms 153 27.27 ms 153 54.54 ms 153 109.08 ms 153 218.16 ms 153 436.32 ms 153 872.64 ms 153 Table W83782D/W83782G 70% RPM TIME FOR 70% 6160 9.74 ms 3080 19.48 ms 1540 38.96 ms 770 77.92 ms 385 155.84 ms 192 311. 623. 1246.72 ms ...
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... GND W83782D FAN Connector Figure 13-4. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp Programmed 8 - bit Register Value = (%) 255 - 15 - W83782D/W83782G +12V Pull-up resister 4.7K Ohms 14K~39K Fan Input 10K Output and Register Attenuator +12V Pull-up resister < totem-pole output > 1K ...
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... G NMOS Figure 14. 8-BIT DIGITAL OUTPUT 8-Bit Hex 7Dh 19h 01h - - 00h - - FFh E7h C9h Table W83782D/W83782G PNP Transistor C FAN 9-BIT DIGITAL OUTPUT 9-Bit Binary 9-Bit Hex 0,1111,1010 0FAh 0,0011,0010 032h 0,0000,0010 002h 0,0000,0001 001h 0,0000,0000 000h 1,1111,1111 1FFh 1,1111,1110 1FFh 1,1100,1110 ...
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... SMI *Interrupt Reset when Interrupt Status Registers are read causes an interrupt and this interrupt will be reset by reading all the O , the interrupt will occur again when the next conversion has HYST - 17 - W83782D/W83782G (Over Temperature) Limit causes (Figure 16- then reset, if the Figure 15-2. Two-Times Interrupt Mode ...
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... OVT# activated indefinitely until reset by reading , the OVT# will not be activated again. (Figure 17) HYST To T HYST * *Interrupt Reset when Temperature 2/3 is read Figure 17. Over-Temperature Response Diagram - 18 - W83782D/W83782G HYST , then reset, if the temperature Figure 16-2. Two-Times Interrupt Mode , then OVT# reset, and then O * ...
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... Bit 6-0: Read/Write Bit 7 Bit 6 Busy (Power On default 0) A6 Port x5h 00h Bit 6:0 Read/write, Bit 7: Read Only 8 bits Bit 5 Bit 4 Bit 3 Address Pointer (Power On default 00h W83782D/W83782G Data Bit 2 Bit 1 Bit Publication Release Date: April 14, 2005 Revision 2.0 ...
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... W83782D/W83782G Notes Auto-increment to the address of Interrupt Status Register 2 after a read or write to Port x6h. Auto-increment to the address of SMIÝ Mask Register 2 after a read or write to Port x6h. Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh ...
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... Bit 6: A one indicates the fan count limit of FAN1 has been exceeded. 40h 00000001 binary Read/write 8 bits START SMI#Enable RESERVED INT_Clear RESERVED RESERVED BEEP/GPO# INITIALIZATION 41h 00h Read Only 8 bits W83782D/W83782G VCOREA VINRO +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Attribute: Size: Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 42h 00h Read Only 8 bits +12VIN -12VIN -5VIN FAN3 Chassis Intrusion Temp3 Reserved Reserved 43h 00h Read/Write 8 bits W83782D/W83782G VCOREA VINRO +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 ...
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... Bit 6-0: Reserved. This bit should be set to 0. 44h 00h Read/Write 8 bits +12VIN -12VIN -5VIN FAN3 Chassis Intrusion TEMP3 Reserved Reserved 46h <7:0> = 00000000 binary Read/Write 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear - 23 - W83782D/W83782G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Serial Bus Address Register − Index 48h Register Location: Power on Default Value Serial Bus address Size Bit 7: Read Only - Reserved. Bit 6-0: Read/Write - Serial Bus address <6:0> VID0 VID1 VID2 VID3 FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 48h <6:0> = 0101101 and <7> binary 8 bits W83782D/W83782G Serial Bus Address Reserved ...
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... High Limit 72h +5VIN Low Limit 73h +12VIN High Limit 74h +12VIN Low Limit 75h -12VIN High Limit 76h -12VIN Low Limit 77h -5VIN High Limit 78h -5VIN Low Limit - 25 - W83782D/W83782G DESCRIPTION Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Note the number of counts of the internal clock for the Low Limit of the fan speed. 7Dh FAN3 Fan Count Limit Note the number of counts of the internal clock for the Low Limit of the fan speed. Reserved 49h <7:1> is 000,0001b <0> is mapped to VID <4> 8 bits W83782D/W83782G DESCRIPTION VID4 DID<6:0> ...
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... ADC clock select 5.6 Khz. (22.5K/4) 4Ah <7:0> = 0000, 0001 binary. Reset by MR Read/Write 8 bits I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3 4Bh Read/Write 8 bits Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1 - 27 - W83782D/W83782G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... OVT1 output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. User Defined. Bit 0: Reserved. User Defined. 4Ch <7:0> --0000,0001. Reset by MR. Read/Write 8 bits Reserved Reserved OVTPOL DIS_OVT1 DIS_OVT2 Reserved T23_INTMode Reserved - 28 - W83782D/W83782G ...
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... FAN control signal and the output value of FAN control is set by this register t 1. This output pin can connect to power PMOS gate to control FAN ON/OFF. 4Dh <7:0> 0001, 0101. Reset by MR. Read/Write 8 bits FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 GPOSEL DIS_ABN - 29 - W83782D/W83782G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. 7.20 Winbond Test Register − Index 50h - 55h (Bank 0) Reserved 4Eh <6:3> = Reserved, <7> <2:0> Reset by MR Read/Write 8 bits BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS 4Fh <15:0> = 5CA3h Read Only 16 bits VIDH VIDL - 30 - W83782D/W83782G ...
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... Register Location: 57h Power on Default Value <7:0> 1000-0000. Reset by MR. Attribute: Read/Write Size: 8 bits 7 56h Read/Write 8 bits EN_VCA_BP EN_Vr0_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP EN_T3_BP Reserved EN_GBP - 31 - W83782D/W83782G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 7: Winbond Chip ID number. Read this register will return 30h. 7.24 Diode Selection Register − Index 59h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 58h Read Only 8 bits 59h <7>=0 and <6:4> = 111 and <3:0> = 0000 Read/Write 8 bits Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved - 32 - W83782D/W83782G CHIPID ...
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... PWMOUT1 Control − Index 5Bh (Bank 0) Register Location: Power on default value: <7:0> 1111-1111. Reset by MR. Attribute: Size: 7 Bit 7: PWMOUT1 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. 5Ah Read/Write 8 bits 5Bh Read/Write 8 bits W83782D/W83782G PWM2_DUTY PWM1_DUTY Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Power on Default Value <7:0> 0000-0000. Reset by MR. Attribute: Size: 7 Bit 7: Fan3 divisor Bit 2. Bit 6: Fan2 divisor Bit 2. Bit 5: Fan1 divisor Bit 2. Bit 4: Reserve. 5Ch Read/Write 8 bits PWM2CLKSEL PWM2CLKSEL PWM2CLKSEL EN_FANPWM2 PWM1CLKSEL PWM1CLKSEL PWM1CLKSEL Reserved 5Dh Read/Write 8 bits EN_VBAT_MNT DIODES1 DIODES2 DIODES3 RESERVE FANDIV1_B2 FANDIV2_B2 FANDIV3_B2 - 34 - W83782D/W83782G ...
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... Power on Default Value <7:0> 1111-1111. Reset by MR. Attribute: Size: 7 Bit 7: PWMOUT3 duty cycle control Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. FAN DIVISOR BIT 5Eh Read/Write 8 bits W83782D/W83782G BIT 1 BIT 0 FAN DIVISOR 128 PWM3_DUTY Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. 7.31 Temperature Sensor 2 Temperature (High Byte) Register − Index 50h (Bank 1) Register Location: 50h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <8:1> of sensor 2, which is high byte. 5Fh Read Only 8 bits W83782D/W83782G PWM4_DUTY TEMP2<8:1> ...
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... Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor TEMP2<0> 52h <7:0> = 0x00 8 bits STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved - 37 - W83782D/W83782G Reserved Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 6-0: Reserved. This bit should be set to 0. 7.36 Temperature Sensor 2 Over-temperature (High Byte) Register − Index 55h (Bank 1) Register Location: Power on Default Value Attribute: Size: 53h <7:0> = 0x4B Read/Write 8 bits 54h Read Only 8 bits 55h <7:0> = 0x50 Read/Write 8 bits - 38 - W83782D/W83782G THYST2<8:1> Reserved THYST2<0> ...
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... Temperature Sensor 3 Temperature (High Byte) Register − Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits 7 6 Bit 7-0: Temperature <8:1> of sensor 2, which is high byte 56h 8 bits W83782D/W83782G TOVF2<8:1> Reserved TOVF2<0> TEMP2<8:1> Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 1: Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor 52h <7:0> = 0x00 8 bits STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved - 40 - W83782D/W83782G Reserved TEMP2<0> ...
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... Power on Default Value <7:0> = 0x0 Attribute: Size: 7 Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0. 53h <7:0> = 0x4B Read/Write 8 bits 54h Read Only 8 bits W83782D/W83782G THYST3<8:1> Reserved THYST3<0> Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Temperature Sensor 3 Over-temperature (Low Byte) Register − Index 56h (Bank 2) Register Location: Power on Default Value <7:0> = 0x0 Size Bit 7: Read/Write- Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only- Reserved. This bit should be set to 0. 55h <7:0> = 0x50 Read/Write 8 bits 56h 8 bits TOVF3<0> W83782D/W83782G TOVF3<8:1> Reserved ...
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... Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. 50h Read Only 8 bits 51h Read/Write 8 bits W83782D/W83782G 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. 53h Read/Write 8 bits EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved 59h Read Only 8 bits VCOREA_STS VINR0_STS +3.3VIN_STS +5VIN_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS - 44 - W83782D/W83782G ...
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... Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range. 5Ah Read Only 8 bits +12VIN_STS -12VIN_STS -5VIN_STS FAN3_STS CASE_STS TEMP3_STS Reserved Reserved - 45 - W83782D/W83782G Publication Release Date: April 14, 2005 Revision 2.0 ...
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... Bit 2-0: PWMOUT3 clock Selection. <2:0> = 000: 46.87K Hz <2:0> = 001: 23.43K Hz (Default) <2:0> = 010: 11.72K Hz <2:0> = 011: 5.85K Hz <2:0> = 100: 2.93K Hz 5Bh Read Only 8 bits 5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved 5Ch Read/Write 8 bits PWM3CLKSEL PWM3CLKSEL PWM3CLKSEL Reserved PWM4CLKSEL PWM4CLKSEL PWM4CLKSEL Reserved - 46 - W83782D/W83782G ...
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... VBAT reading 52h Reserved 53h Reserved 54h 5VSB High Limit 55h 5VSB Low Limit. 56h VBAT High Limit 57h VBAT Low Limit 7.54 Winbond Test Register − Index 50h (Bank 6) Reserved. DESCRIPTION Publication Release Date: April 14, 2005 - 47 - W83782D/W83782G Revision 2.0 ...
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... TTL level bi-directional pin with source-sink capability and schmitt-trigger 12ts level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage W83782D/W83782G RATING -0.5 to 7 +70 -55 to +150 SYM. MIN. ...
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... TTL level input pin t Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - TTL level Schmitt-triggered input pin ts Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage W83782D/W83782G SYM. MIN. TYP. MAX ...
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... AC Characteristics 8.3.1 ISA Read/Write Interface Timing AEN SA[2:0],CS IOR# IOW# SD[7:0] IRQ AEN SA[2:0],CS IOW# IOR# SD[7:0] IRQ W83782D/W83782G VALID DATA t RVD t RDH t RI ISA Bus Read Timing VALID VALID DATA ISA Bus Write Timing - RCU VALID t WCU ...
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... Read Cycle Update Read Strobe Width Read Data Hold Read Strobe to Clear IRQ Active Read to Valid Data Address Hold from Inactive Write Write Cycle Update Write Strobe to Clear IRQ Write Strobe Width Read Cycle = RCV Write Cycle = WCV W83782D/W83782G SYMBOL MIN 200 ...
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... PARAMETER SCL Clock Period Start Condition Hold Time Stop Condition Setup-up Time DATA to SCL Setup Time DATA to SCL Hold Time SCL and SDA Rise Time SCL and SDA Fall Time W83782D/W83782G t SCL t HD;DAT VALID DATA t SU;DAT Serial Bus Timing Diagram SYMBOL MIN ...
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... The top marking of W83782G W83782G 825AA Left: Winbond logo 1st line: Type number W83782G, G means Lead-free Package. 2nd line: Tracking code 825: packages made in '98, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B ...
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... PACKAGE DIMENTIONS 48-pin QFP See Detail F Seating Plane Detail W83782D/W83782G Dimension in inch Dimension in mm Symbol Min. Nom. Nom. Max. Min. A --- --- A 0.05 --- 1 A 1.35 1. 0.20 0.17 c --- 0.09 D 7.00 E 7.00 e 0. 0.45 0. --- 0.08 0 3.5 0 Notes: 1. Dimensions D & not include interlead flash ...
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... CPU Voltage ID output 3VCC R12 R13 R14 R15 R16 10K 10K 10K 10K 10K VID4 PIIVID4 VID3 PIIVID3 VID2 PIIVID2 VID1 PIIVID1 VID0 PIIVID0 - 55 - W83782D/W83782G U1 R25 R RSTOUT# 0 /781D 24 VID2 R26 R 23 PWMOUT1 22 SDA 0 /782D 21 SCL 20 FAN1IN 19 FAN2IN R29 R 18 PWMOUT2 17 VID4 0/782D ...
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... Q4 R55 R MOSFET N PWMOUT2 510/782D 2N7002/782D (for system) (from PII CPU) (for cpu2) R70 R69 CASEOPEN 10K/781D 0/781D U2B 4 3 74HC14 /781D - 56 - W83782D/W83782G +12V R60 Q7 D1 0/781D R PNP DIODE R45 3906/782D 1N4148 R 4.7K R61 R C9 JP2 0/782D R46 R 47u/782D + 3 2 27K ...
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... Rev. Description 0.1 First published. 0.2 Change CASEOPEN circuit for W83781D/782D co-layout. 0.3 Change 2N3904 in Fan Speed Control circuit to 2N7002. W83782D/W83782G Winbond Electronic Corp. Title Size B Date: Publication Release Date: April 14, 2005 - 57 - W83781D-W83782D Application Circuit Document Number Rev 0.3 Thursday, July 23, 1998 ...
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... April 14, 2005 W83782D/W83782G PAGE DESCRIPTION All the version before 0.50 are for internal n.a. use. n.a. First publication. Add the content of Diode Selection Register P.40 Index 59h(Bank0) Add the content of VBAT Monitor Control P ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83782D/W83782G Important Notice Publication Release Date: April 14, 2005 - 59 - Revision 2.0 ...