ADT7462ACPZ-REEL ON Semiconductor, ADT7462ACPZ-REEL Datasheet - Page 52

• Manufacturer Part Number: ADT7462ACPZ-REEL
• Description: IC TEMP/VOLT MONITOR 32-LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADT7462ACPZ-REEL

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Number Of Voltages Monitored: 1
• Monitored Voltage: 0.9 V to 12 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (typ): 4000 uA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 4 (VRD2) of Configuration Register 2 (0x02). There is
also an associated mask bit in Register 0x31 to mask the
assertion of these inputs from the ALERT output.
SCSI_TERM Inputs
inputs. An assertion on the SCSI_TERM is recorded in Bit 4
and Bit 5 of Host Digital Status Register (0xBE) or BMC
Digital Status Register (0xC6). There is also an associated
mask bit in Register 0x35 to mask the assertion of these
inputs from the ALERT output.
Reset I/O
The RESET pin can be both a reset input and output. RESET
monitors the V
RESET is asserted (pulled low) until 180 ms after the power
supply has risen above the supply threshold. A power−on
reset initializes all registers to the default values.
this pin low externally resets the ADT7462. The user should
wait at least 180 ms after powerup before doing a hardware
reset. The reset pulse width should be greater than 0.8 ms to
ensure that a reset is registered.
all of the registers are reinitialized to the default values. For
example, limit registers are not all restored to the default
values. This can be useful if the user needs to reset the part
but does not want to completely reprogram the device. The
Register Map section show, which registers, are reset.
Locked registers are not restored to default values by a
hardware reset.
the RESET pins should not be connected together between
devices. Doing so causes one device to reset the other on a
power−on reset.
Software Reset
Configuration Register 0 (0x00). The code 0x6D must be
written to Register 0x7B before setting the software reset bit.
This register is cleared to the power−on default after the
software reset.
values on a reset. The same registers are reset by a hardware
and software reset. The Register Map section provides a
complete reference of registers that are reset.
RESET
Figure 85. Operation of RESET Output on Powerup
Pin 16 and Pin 20 can be configured as SCSI_TERM
The ADT7462 includes an active low reset pin (Pin 14).
The RESET pin can also function as a reset input. Pulling
A hardware reset differs from a power−on reset in that not
Note that if two ADT7462 devices are used in one system,
The ADT7462 can be reset in software by setting Bit 7 of
Note that not all registers are restored to their default
V
CC
1.0 V
CC
180 ms
input to the ADT7462. At powerup,
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52
Chassis Intrusion Input
intended for detection and signaling of unauthorized
tampering with the system. When this input goes high, the
event is latched in Bit 7 of Host Digital Status Register
(0xBE), and an interrupt is generated. The bit remains set
until cleared by writing a 1 to CI reset (CI_R), Bit 5 of
Configuration Register 3 (0x03). The CI reset bit is cleared
by writing a 0 to it.
channel. Pin 26 must be configured to monitor V
a battery must be connected to monitor CI events. CI
monitoring is disabled if the measured V
is less than the lower voltage limit (0x75) of Pin 26.
the ADT7462 is powered off (provided battery voltage is
applied to V
interrupt. When a chassis intrusion event is detected and
latched, an interrupt is generated when the system is
powered on.
an external circuit that detects, for example, when the cover
has been removed. A wide variety of techniques can be used
for chassis detection. For example,
•
•
•
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Powerup Sequence
The chassis intrusion (CI) input is an active high input
The CI circuit is powered from the V
The CI input detects chassis intrusion events even when
The actual detection of chassis intrusion is performed by
The powerup sequence of the ADT7462 is as follows:
A microswitch that opens or closes when the cover is
removed
A reed switch operated by a magnet affixed to the cover
A hall−effect switch operated by a magnet affixed to
the cover
A photo−transistor that detects light when the cover is
removed
1. The temperature of the thermal diode connected to
2. V
3. V
4. PWM1, PWM2, and PWM4 are not on dedicated
Pin 17 and Pin 18 (only dedicated thermal diode
channel) is monitored immediately on powerup of
the ADT7462. Ideally, the hottest zone should be
connected to this channel so protection is provided
immediately on powerup.
V
Switching on the V
startup counter.
before the setup complete bit (Register 0x01,
Bit 5) is set. The chassis intrusion circuit (CI) is
powered from V
reading is lower than the lower limit (default =
0x80), the CI circuit is turned off.
pins. Because these pins are shared with inputs,
they are allowed to float high on powerup. This
means that if a fan is connected to these pins, it
spins at full speed on powerup.
CCP1
CCP1
BATT
BATT
is also monitored immediately on powerup.
is typically connected to a main power rail.
is monitored immediately on powerup
) but does not immediately generate an
BATT
CCP1
. If the measured V
rail gates the fan’s quiet
BATT
BATT
value (0x93)
BATT
BATT
voltage
and