ADT7461ARMZ-2REEL ON Semiconductor, ADT7461ARMZ-2REEL Datasheet - Page 12

• Manufacturer Part Number: ADT7461ARMZ-2REEL
• Description: IC SENSOR TEMP DGTL 2CH 8MSOP
• Manufacturer: ON Semiconductor

Specifications of ADT7461ARMZ-2REEL

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 127°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Writing to Address ox0F causes the ADT7461 to perform a single measurement. It is not a data register, therefore, data written to it is
Serial Bus Interface
The ADT7461 is connected to this bus as a slave device,
under the control of a master device.
no SMBus transactions to the ADT7461 for at least one
conversion time, to allow the next conversion to complete.
The conversion time depends on the value programmed in
the conversion rate register.
is enabled, the SMBus times out typically after 25 ms of
inactivity. However, this feature is not enabled by default.
Bit 7 of the consecutive alert register (Address = 0x22)
should be set to enable it.
information (www.smbus.org).
Addressing the Device
address, except for some devices that have extended 10-bit
addresses. When the master device sends a device address
over the bus, the slave device with that address responds.
The ADT7461 is available with one device address, 0x4C
(1001 100b). The ADT7461-2 is also available with one
device address, 0x4D (1001 101b)
Table 8. List of Registers
Read Address (Hex)
Not applicable
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Not applicable
0x10
0x11
0x12
0x13
0x14
0x19
0x20
0x21
0x22
0xFE
0xFF
Control of the ADT7461 is carried out via the serial bus.
After a conversion sequence completes, there should be
The ADT7461 has an SMBus timeout feature. When this
Consult the SMBus 1.1 specification for more
In general, every SMBus device has a 7-bit device
irrelevant.
Write Address (Hex)
Not applicable
Not applicable
Not applicable
Not applicable
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F (Note 1)
Not applicable
0x11
0x12
0x13
0x14
0x19
0x20
0x21
0x22
Not applicable
Not applicable
Address Pointer
Local Temperature Value
External Temperature Value High Byte
Status
Configuration
Conversion Rate
Local Temperature High Limit
Local Temperature Low Limit
External Temperature High Limit High Byte
External Temperature Low Limit High Byte
One-Shot
External Temperature Value Low Byte
External Temperature Offset High Byte
External Temperature Offset Low Byte
External Temperature High Limit Low Byte
External Temperature Low Limit Low Byte
External THERM Limit
Local THERM Limit
THERM Hysteresis
Consecutive ALERT
Manufacturer ID
Die Revision Code
http://onsemi.com
12
Name
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
2. Data is sent over the serial bus in a sequence of
start condition, defined as a high-to-low transition
on the serial data line SDATA, while the serial
clock line SCLK remains high. This indicates that
an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an
R/W bit, which determines the direction of the
data transfer, that is, whether data will be written
to or read from the slave device. The peripheral
whose address corresponds to the transmitted
address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the acknowledge bit. All other devices
on the bus now remain idle while the selected
device waits for data to be read from or written to
it. If the R/W bit is a 0, the master writes to the
slave device. If the R/W bit is a 1, the master reads
from the slave device.
nine clock pulses, eight bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period
of the clock signal and remain stable during the
Undefined
0000 0000 (0x00)
0000 0000 (0x00)
Undefined
0000 0000 (0x00)
0000 1000 (0x08)
0101 0101 (0x55) (85°C)
0000 0000 (0x00) (0°C)
0101 0101 (0x55) (85°C)
0000 0000 (0x00) (0°C)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 1100 (0x55) (85°C)
0101 0101 (0x55) (85°C)
0000 1010 (0x0A) (10°C)
0000 0001 (0x01)
0100 0001 (0x41)
0101 0001 (0x51)
Power−On Default