IR3651STRPBF International Rectifier, IR3651STRPBF Datasheet - Page 15

• Manufacturer Part Number: IR3651STRPBF
• Description: IC CTLR PWM SYNC DC-DC 14SOIC
• Manufacturer: International Rectifier

Specifications of IR3651STRPBF

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 460kHz
• Duty Cycle: 80%
• Voltage - Supply: 4.5 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 125°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 460kHz
• Package: 14-Pin SOIC (NB)
• Circuit: Sync PWM Controller
• Vcc (min): 4.5
• Vcc (max): 13.2
• Iout (a): 25
• Switch Freq (khz): programmable to 400kHz
• Pbf: PbF Option Available
• For Use With: IRDC3651 - KIT REF DESIGN SYNCH BUCK REG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Feedback Compensation
The IR3651 is a voltage mode controller; the
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180
(see figure 11). The resonant frequency of the LC
filter expressed as follows:
Figure 11 shows gain and phase of the LC filter.
Since we already have 180
the output filter, the system risks being unstable.
The IR3651’s error amplifier is a differential-input
transconductance
available for DC gain control or AC phase
compensation.
The error amplifier can be compensated either in
typeII or typeIII compensation. When it is used in
typeII
properties of the error amplifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 12.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
12/07/2010
0dB
Gain
Fig. 11: Gain and Phase of LC filter
F
LC
compensation
=
F
2
LC
∗
π
Frequency
-40dB/decade
1
L
o
∗
amplifier.
C
o
-180
the
-
0
Phase
-(11)
o
phase shift just from
transconductance
The
F
LC
output
Frequency
o
).
is
o
The ESR zero of the output capacitor is
expressed as follows:
The transfer function (Ve/Vo) is given by:
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-crossover frequency
(Fo):
Use the following equation to calculate R4:
Where:
V
V
F
F
F
R
g
m
o
ESR
LC
in
osc
8
= Crossover Frequency
and R
= Error Amplifier Transconductance
= Maximum Input Voltage
= Resonant Frequency of the Output Filter
V
= Oscillator Ramp Voltage
H
= Zero Frequency of the Output Capacitor
H(s) dB
O
Fig. 12: TypeII compensation network
(
R
R
s
8
9
R
)
9
=
F
V
3
= Feedback Resistor Dividers
o
REF
=
Fb
Gain(dB)
⎛
⎜ ⎜
⎝
and its asymptotic gain plot
F
>
g
ESR
V
[
F
H
m
F
z
osc
*
( )
ESR
=
=
s
V
*
R
2
2
]
in
F
9
and
π
=
R
o
E/A
∗
*
+
*
9
⎛
⎜ ⎜
⎝
*
F
π
F
R
g
F
R
LC
1
2
Z
F
*
8
ESR
m
3
o
ESR
⎞
⎟ ⎟
⎠
*
1
*
*
R
*
≤
Frequency
( *
R
C
Comp
1
IR3651SPBF
9
(
9
1/5
4
R
*
+
R
+
*
8
sC
g
sR
9
R
C
R
+
m
C
~
3
o
4
8
R
3
-
4
1/10
C
⎞
⎟ ⎟
⎠
9
Ve
-(14)
*
4
)
-
R
-(12)
3
)
-
*
-
-(13)
C
F
-(15)
POLE
s
15