NCP1338DR2G ON Semiconductor, NCP1338DR2G Datasheet - Page 11

• Manufacturer Part Number: NCP1338DR2G
• Description: IC CTRLR PWM CM OVP 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1338DR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 130kHz
• Voltage - Supply: 11 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width, 7 Lead)
• Frequency-max: 130kHz
• Output Voltage: - 0.3 V to + 20 V
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Fall Time: 20 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 50 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Soxyless
of the Power MOSFET Drain voltage variations. When the
transformer is fully demagnetized, the Drain voltage
evolution from the plateau level down to the V
is governed by the resonating energy transfer between the
L
on the Drain. These voltage oscillations create current
oscillation in the parasitic capacitor across the switching
Igate = Vringing/Zc (with Zc the capacitance impedance)
so
Igate = Vringing S (2 S p S Fres S Crss)
MOSFET, the resonating frequency and the voltage swing
present on the Drain at the end of the plateau voltage.
(where L
C
P
DRAIN
The “Valley point detection” is based on the observation
The current in the Power MOSFET gate is:
The magnitude of this gate current depends on the
The dead time T
transformer inductor and the global capacitance present
the total capacitance present on the MOSFET
Tswing + 0.5 Fres + p * Lp * Cdrain
P
is the primary transformer inductance and
DRV
SWING
Isoxy
FB
is given by the equation:
Crss
3 V
+
Figure 7. Internal Implementation of FB Pin
+
-
Lprim
IN
Figure 6. Soxyless Concept
asymptote
http://onsemi.com
(eq. 1)
Low−pass Filter
Vswitch
11
20 kHz
MOSFET (modelized by the Crss capacitance between
Gate and Drain): a negative current (flowing out of DRV
pin) takes place during the decreasing part of the Drain
oscillation, and a positive current (entering into the DRV
pin) during the increasing part.
current (i.e., the zero crossing): by detecting this point, we
always ensure a true valley turn−on.
Drain. This capacitance includes the snubber capacitor if
any, the transformer windings stray capacitance plus the
parasitic MOSFET capacitances C
Internal Feedback Circuitry
it is necessary to inject a current into the FB pin (instead of
sourcing it out). But to have a precise primary regulation,
the voltage present on FB pin must be regulated. Figure 8
gives the FB pin internal implementation: the circuitry
combines the functions of a current to voltage converter
and a voltage regulator.
The Drain valley corresponds to the inversion of the
To simplify the implementation of a primary regulation,
Vdd
T
SWING
Internal
Setpoint
OSS
t
and C
RSS
).