NCP1378DR2G ON Semiconductor, NCP1378DR2G Datasheet - Page 8

• Manufacturer Part Number: NCP1378DR2G
• Description: IC CTRLR PWM CM OVP UVLO 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1378DR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 100kHz
• Voltage - Supply: 8.2 V ~ 18 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 100kHz
• Output Voltage: 16 V
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 100 KHz
• Operating Supply Voltage: 18 V
• Maximum Operating Temperature: + 150 C
• Fall Time: 20 ns
• Rise Time: 40 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1378DR2GOS; NCP1378DR2GOS; NCP1378DR2GOSTR

constrained below 16 V, which is the maximum rating on
pin 6. Figure 16 portrays a typical NCP1378 startup
sequence with a Vcc regulated at 8.0 V.
inserted between the current sense input and the sense
element. Every time the NCP1378 output driver goes low,
a 200 mA source forces a current to flow through the sense
pin (Figure 18): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200 mA and develops a ground referenced
voltage across Rskip. If this voltage is below the feedback
voltage, the current sense comparator stays in the low state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
Once the power supply has started, the Vcc shall be
The skip level selection is done through a simple resistor
9.0
8.0
7.0
6.0
5.0
300
200
100
0
Figure 17. The Skip Cycle Takes Place at Low Peak
3.00M
Figure 16. A Typical Startup Sequence
Currents which Guarantees Noise- -Free Operation
8.4 V
RECURRENCE
MAX PEAK
CURRENT
8.00M
for the NCP1378
Normal Current Mode Operation
WIDTH
time in secs
13.0M
18.0M
CURRENT LIMIT
Regulation
SKIP CYCLE
23.0M
http://onsemi.com
8
Skipping Cycle Mode
when the output power demand drops below a given
level. This is accomplished by monitoring the FB pin. In
normal operation, pin 2 imposes a peak current accordingly
to the load value. If the load demand decreases, the internal
loop asks for less peak current. When this setpoint reaches
a determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so- - called skip cycle mode, also
named controlled burst operation. The power transfer
now depends upon the width of the pulse bunches
(Figure 17)
Lp = Primary inductance
Fsw = Switching frequency within the burst
Ip = Peak current at which skip cycle occurs
D
voltage is below Rskip level, then the current sense
comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown by Figure 17. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1378. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator alone initiates a
new cycle start. Figure 19 depicts these two different
situations.
1
2
burst
The NCP1378 automatically skips switching cycles
RESET
· Lp · Ip 2 · Fsw · D burst
Level Selection via a Series Resistor Inserted in
Figure 18. A Patented Method Allows for Skip
= Burst width/burst recurrence
and
+
Series with the Current
- -
follows
+
3
2
with:
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200 mA
the
following
R
skip
R
formula:
sense