LTC3714EG Linear Technology, LTC3714EG Datasheet - Page 18
![IC STP-DWN CNTRLR W/OPAMP 28SSOP](/photos/6/59/65971/161-28-ssop_sml.jpg)
LTC3714EG
Manufacturer Part Number
LTC3714EG
Description
IC STP-DWN CNTRLR W/OPAMP 28SSOP
Manufacturer
Linear Technology
Datasheet
1.LTC3714EGPBF.pdf
(22 pages)
Specifications of LTC3714EG
Applications
Controller, Intel Pentium®
Voltage - Input
4 ~ 36 V
Number Of Outputs
1
Voltage - Output
0.6 ~ 1.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC3714EG
Manufacturer:
LT/凌特
Quantity:
20 000
Part Number:
LTC3714EG#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC3714EG#TR
Manufacturer:
LT
Quantity:
19
Company:
Part Number:
LTC3714EG#TRPBF
Manufacturer:
LUNGE
Quantity:
900
Part Number:
LTC3714EG#TRPBF
Manufacturer:
LT/凌特
Quantity:
20 000
applicaTions inForMaTion
LTC3417A
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3417A. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
1. Does the capacitor C
2. Are the C
3. The resistor divider, R1 and R2, must be connected
18
(Pin 2), V
close as possible (DFN package)? It may be necessary
to split C
the AC current to the internal power MOSFETs and
their drivers.
(–) plate of C
(–) plate of C
and the (–) plate of C
between the (+) plate of C
minated near GNDA. The resistor divider, R3 and R4,
IN
OUT1
IN2
into two capacitors. This capacitor provides
OUT2
, L1 and C
OUT1
(Pin 8), and PGND2/GNDD (Pin 17) as
returns current to the PGND2/GNDD
returns current to PGND1, and the
IN
STAR TO
IN
OUT2
GNDA
.
C
V
OUT2
OUT2
connect to the power V
V
V
IN
IN
OUT1
, L2 closely connected? The
10µF
C
IN
and a ground line ter-
C
ITH2
C
0.1µF
C2
C
R
IN2
R3
R4
R8
L2
ITH2
Figure 5. Layout Guideline
V
PGND2/
EXPOSED PAD
GNDA
SW2
V
I
PGOOD
RUN2
PHASE
TH2
IN2
FB2
IN1
LTC3417A
GNDD
SYNC/MODE
4. Keep sensitive components away from the SW pins.
5. A ground plane is preferred, but if not available, keep
6. Flood all unused areas on all layers with copper. Flooding
PGND1
must be connected between the (+) plate of C
a ground line terminated near GNDA. The feedback
signals V
components and traces, such as the SW lines, and its
trace should be minimized.
The input capacitor C
C
R4, R
SW traces and the inductors L1 and L2.
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the PGND2/GNDD
pin.
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
RUN1
FREQ
SW1
V
V
C1
I
TH1
FB1
IN1
, C
ITH1
C2
, C
FB1
and R
R
ITH1
R1
R2
R7
L1
ITH1
C
0.1µF
and V
IN1
C
C1
C
and C
ITH1
ITH2
FB2
should be routed away from noise
should be routed away from the
ITH2
IN
C
V
OUT1
OUT1
, the compensation capacitors
STAR TO
V
IN
GNDA
and all resistors R1, R2, R3,
OUT2
3417afc
and