LTC3831EGN-1 Linear Technology, LTC3831EGN-1 Datasheet - Page 11

• Manufacturer Part Number: LTC3831EGN-1
• Description: IC CTRLR SW REG SYNC DDR 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC3831EGN-1

• Applications: Controller, DDR
• Voltage - Input: 3 ~ 8 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SYNC METHOD
TERMINATION
UNDER SYNC
Input Supply Considerations/Charge Pump
The LTC3831-1 requires four supply voltages to operate:
V
FET gate drive and a clean, low ripple V
internal circuitry (Figure 4). V
V
The V
current is typically 800 A. Place a 4.7 A bypass capacitor
as close as possible to this pin. Gate drive for the top
N-channel MOSFET Q1 is supplied from PV
APPLICATIO S I FOR ATIO
external clock frequency goes higher. The effect of this
decrease in ramp amplitude increases the open-loop gain
of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feed-
back loop to be unstable if the phase margin is insufficient.
To overcome this problem, the LTC3831-1 monitors the
peak voltage of the ramp signal and adjust the oscillator
charging current to maintain a constant ramp peak.
TRADITIONAL
KEEPS RAMP
WITH EARLY
AMPLITUDE
IN
DDQ
CONSTANT
LTC3831
for the main power input, PV
RAMP
RAMP AMPLITUDE
in most DDR memory termination applications.
CC
Figure 3. External Synchronization Operation
supply can be as low as 3V and the quiescent
SHDN
FREE RUNNING
ADJUSTED
RAMP SIGNAL
200kHz
U
U
IN
CC1
is usually connected to
W
and PV
CC
for the LTC3831-1
WITH EXT SYNC
RAMP SIGNAL
CC2
U
CC1
for MOS-
. This
38311 F03
supply must be above V
V
must be higher that V
tion. An internal level shifter allows PV
voltages above V
higher voltage can be supplied with a separate supply, or
it can be generated using a charge pump.
Gate drive for the bottom MOSFET Q2 is provided through
PV
MOSFET V
driven from the same supply/charge pump for the PV
or it can be connected to a lower supply to improve
efficiency.
In a typical low voltage DDR memory termination applica-
tion, V
supply for the LTC3831-1 is 3.3V, a tripling charge pump
circuit can be added to power the PV
This requires sub-logic level threshold power MOSFET
with R
Figure 5 shows a tripling charge pump circuit that powers
the PV
2V
to PV
The circuit requires the use of Schottky diodes to minimize
forward drop across the diodes at start-up. The tripling
charge pump circuit will tend to rectify any ringing at the
drain of Q2 and can provide well more than (V
at PV
to PGND to prevent transients from damaging the circuitry
at PV
GS(ON)
IN
LTC3831-1
CC2
– 3V
CC1
CC2
CC1
CIRCUITRY
INTERNAL
. This supply only needs to be above the power
IN
DS(ON)
CC1
V
. A 12V zener diode may be included from PV
for efficient operation. In addition, this supply
or V
CC
where V
or the gate of Q1.
F
GS(ON)
) to PV
and PV
DDQ
specified at V
can be a low as 1.5V. If the only available
CC1
F
for efficient operation. PV
PV
CC
Figure 4. Input Supplies
CC2
is the ON voltage of the Schottky diode.
CC2
and V
while Q1 is ON and (V
CC
pins. This circuit provides (V
IN
PV
by at least 2V for normal opera-
CC1
by at least one power MOSFET
IN
GS
, up to 14V maximum. This
= 2.5V.
BG
TG
V
IN
CC1
LTC3831-1
Q1
Q2
CC1
and PV
L
CC2
CC
O
to operate at
+ V
can also be
+
CC
CC2
IN
38311 F04
11
+ 2V
C
– 2V
OUT
pins.
V
CC
38311f
CC1
OUT
CC1
IN
F
+
)
)
,