ADP3208CJCPZ-RL ON Semiconductor, ADP3208CJCPZ-RL Datasheet - Page 30

• Manufacturer Part Number: ADP3208CJCPZ-RL
• Description: IC CTLR BUCK 7BIT IMVP6 48LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3208CJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Output Voltage: 10 mV
• Output Current: 40 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L
enough to avoid ringing during a load change. If the L
the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased to prevent
excessive ringing.
capacitor design can be used if the conditions of Equations
16, 17, and 18 are satisfied.
Power MOSFETs
power MOSFETs are selected for two high−side switches
and two or three low−side switches per phase. The main
selection parameters for the power MOSFETs are V
Q
gate driver is 5.0 V, logic−level threshold MOSFETs must be
used.
requirement for the low−side (synchronous) MOSFETs. In
the ADP3208C, currents are balanced between phases; the
current in each low−side MOSFET is the output current
divided by the total number of MOSFETs (n
conduction losses being dominant, the following expression
shows the total power that is dissipated in each synchronous
MOSFET in terms of the ripple current per phase (I
the average total output current (I
P
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
I
approximately:
allowed power dissipation, the user can calculate the required
R
SOIC−compatible MOSFETs, the junction−to−ambient
(PCB) thermal impedance is 50°C/W. In the worst case, the
PCB temperature is 70°C to 80°C during heavy load
operation of the notebook, and a safe limit for P
W to 1.0 W at 120°C junction temperature. Therefore, for this
example (40 A maximum), the R
than 8.5 mW for two pieces of low−side MOSFETs. This
R
therefore, the R
at room temperature, or 8.5 mW at high temperature.
is the input capacitance and feedback capacitance. The ratio
of the feedback to input must be small (less than 10% is
recommended) to prevent accidentally turning on the
synchronous MOSFETs when the switch node goes high.
R
SF
X
DS(ON)
DS(SF)
G
For this multi−mode control technique, an all ceramic
For typical 20 A per phase applications, the N−channel
The maximum output current, I
where:
Knowing the maximum output current and the maximum
Another important factor for the synchronous MOSFET
, C
is about 150 pH for the six SP capacitors, which is low
is the inductor peak−to−peak ripple current and is
+ (1 * D)
ISS
is also at a junction temperature of about 120°C;
, C
for the MOSFET. For 8−lead SOIC or 8−lead
RSS
DS(SF)
, and R
I
R
+
n
I
SF
O
( 1 * D )
per MOSFET should be less than 6 mW
DS(ON)
2
L
) 1
12
f
SW
. Because the voltage of the
V
DS(SF)
OUT
O
O
, determines the R
):
n
n
SF
per MOSFET is less
I
R
2
SF
is about 0.8
R
SF
DS(SF)
(eq. 19)
(eq. 20)
). With
GS(TH)
DS(ON)
http://onsemi.com
R
) and
X
of
,
30
two main power dissipation components: conduction losses
and switching losses. Switching loss is related to the time for
the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed
on the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression
provides an approximate value for the switching loss per
main MOSFET:
n
R
C
lower gate capacitance devices.
following equation:
device for a main MOSFET, but such a device usually has
higher on resistance. Therefore, the user must select a device
that meets the total power dissipation (about 0.8 W to 1.0 W
for an 8−lead SOIC) when combining the switching and
conduction losses.
main MOSFET (four in total; that is, n
approximately C
(max at T
as the synchronous MOSFET (four in total; that is, n
with R
power dissipation per MOSFET at I
yields 630 mW for each synchronous MOSFET and
590 mW for each main MOSFET. A third synchronous
MOSFET is an option to further increase the conversion
efficiency and reduce thermal stress.
each phase. This is best described in terms of the Q
MOSFETs and is given by the following equation:
where Q
and Q
MOSFET.
R
R
P
MF
RPM
G
ISS
RPM
The high−side (main) MOSFET must be able to handle
where:
The most effective way to reduce switching loss is to use
The conduction loss of the main MOSFET is given by the
Typically, a user wants the highest speed (low C
For example, an IRF7821 device can be selected as the
Finally, consider the power dissipation in the driver for
DRV
is the total gate resistance.
where R
is the total number of main MOSFETs.
is the input capacitance of the main MOSFET.
+
+
+
DS(SF)
GSF
2
GMF
V
1.150 V ) 1.0 V
f
SW
J
VID
2
= 120°C), and an IR7832 device can be selected
is the total gate charge for each synchronous
2
n
DS(MF)
= 6.7 mW (max at T
is the total gate charge for each main MOSFET,
280 kW
R
1.0 V
ISS
T
n
MF
= 1010 pF (max) and R
is the on resistance of the MOSFET.
A
Q
R
GMF
R
0.5
462 kW
R
( 1 * D )
) n
C
( 1 * 0.061 )
J
R
SF
= 120°C). Solving for the
O
5 pF
f
= 40 A and I
SW
Q
V
* 500 kW + 202 kW
QSF
VID
300 kHz
DS(MF)
* 0.5 kW
MF
) I
1.150
= 4), with
CC
R
= 18 mW
G
(eq. 22)
(eq. 23)
SF
= 9.0 A
(eq. 21)
for the
= 4),
V
ISS
CC
)