MAX8727ETB+TG104 Maxim Integrated Products, MAX8727ETB+TG104 Datasheet - Page 11

IC DC/DC CONV TFT-LCD 10-TDFN

MAX8727ETB+TG104

Manufacturer Part Number
MAX8727ETB+TG104
Description
IC DC/DC CONV TFT-LCD 10-TDFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX8727ETB+TG104

Applications
Converter, TFT, LCD
Voltage - Input
2.6 ~ 5.5 V
Number Of Outputs
1
Voltage - Output
2.6 ~ 24 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-TDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 3. Multiple-Output TFT-LCD Power Supply
Figure 3 shows a power supply for active-matrix TFT-
LCD flat-panel displays. Output-voltage transient perfor-
mance is a function of the load characteristic. Add or
remove output capacitance (and recalculate compensa-
tion-network component values) as necessary to meet
the required transient performance. Regulation perfor-
mance for secondary outputs (V2 and V3) depends on
the load characteristics of all three outputs.
Careful PC board layout is important for proper operation.
Use the following guidelines for good PC board layout:
1) Minimize the area of high-current loops by placing
Multiple-Output Power Supply for TFT LCD
the inductor, rectifier diode, and output capacitors
near the input capacitors and near the LX and GND
pins. The high-current input loop goes from the
positive terminal of the input capacitor to the induc-
tor, to the IC’s LX pin, out of GND, and to the input
capacitor’s negative terminal. The high-current out-
put loop is from the positive terminal of the input
capacitor to the inductor, to the rectifier diode (D1),
4.5V TO 5.5V
PC Board Layout and Grounding
V
10μF
IN
6.3V
______________________________________________________________________________________
C1
+28V C9
V2
1μF
10Ω
1μF
C5
R4
33nF
C4
TFT-LCD Step-Up DC-DC Converter
10
8
9
3
D2
IN
FREQ
SHDN
SS
3.6μH
L1
LX
6
0.1μF
C7
MAX8727
0.1μF
C8
LX
COMP
7
GND
GND
D1
FB
D3
2
5
4
1
2) Create a power ground island (PGND) consisting of
R3
100kΩ
C3
330pF
R1
309kΩ
1%
R2
28.0kΩ
1%
and to the positive terminal of the output capacitors,
reconnecting between the output capacitor and
input capacitor ground terminals. Connect these
loop components with short, wide connections.
Avoid using vias in the high-current paths. If vias
are unavoidable, use many vias in parallel to
reduce resistance and inductance.
the input and output capacitor grounds and GND
pins. Connect all of these together with short, wide
traces or a small ground plane. Maximizing the
width of the power ground traces improves efficien-
cy and reduces output voltage ripple and noise
spikes. Create an analog ground plane (AGND)
consisting of the feedback-divider ground connec-
tion, the COMP and SS capacitor ground connec-
tions, and the device’s exposed backside pad.
Connect the AGND and PGND islands by connect-
ing the GND pins directly to the exposed backside
pad. Make no other connections between these
separate ground planes.
C10
1μF
C6
39pF
V3
-14V
C2
4.7μF
25V
C7
4.7μF
25V
C8
4.7μF
25V
V
15V/600mA
OUT
11

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