MAX17003ETJ+ Maxim Integrated Products, MAX17003ETJ+ Datasheet - Page 23

• Manufacturer Part Number: MAX17003ETJ+
• Description: IC PS CTRLR FOR NOTEBOOKS 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17003ETJ+

• Applications: Controller, Notebook Computers
• Voltage - Input: 6 ~ 26 V
• Number Of Outputs: 4
• Voltage - Output: 3.3V, 5V, 2 ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

maximum load current is less than the peak current-
limit threshold by an amount equal to half of the induc-
tor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
(V
In forced-PWM mode, the MAX17003/MAX17004 also
implement a negative current limit to prevent excessive
reverse inductor currents when V
The negative current-limit threshold is set to approxi-
mately 120% of the positive current limit and tracks the
positive current limit when ILIM is adjusted.
Connect ILIM to LDO5 for the 50mV default threshold,
or adjust the current-limit threshold with an external
resistor-divider at ILIM. Use a 2µA to 20µA divider cur-
rent for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10th the voltage seen at ILIM. The
logic threshold for switchover to the default value is
approximately V
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the differential
current-sense signals seen by CSH_ and CSL_. Place
the IC close to the sense resistor with short, direct
traces, making a Kelvin-sense connection to the cur-
rent-sense resistor.
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V
V
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
charge pumps at BST_ while the DL_ synchronous-rec-
tifier drivers are powered directly by the fixed 5V linear
regulator (LDO5).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead-time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX17003/MAX17004
OUT
OUT
/V
differential exists. The high-side gate drivers
IN
).
Supply Controllers for Notebook Computers
High-Efficiency, Quad-Output, Main Power-
MOSFET Gate Drivers (DH_, DL_)
LDO5
______________________________________________________________________________________
- 1V.
OUT
is sinking current.
IN
-
Applications with high input voltages and long inductive
driver traces may require additional gate-to-source
capacitance to ensure fast-rising LX_ edges do not pull
up the low-side MOSFETs gate, causing shoot-through
currents. The capacitive coupling between LX_ and DL_
created by the MOSFET’s gate-to-drain capacitance
(C
- C
exceed the following minimum threshold:
Lot-to-lot variation of the threshold voltage may cause
problems in marginal designs.
PGDALL is the open-drain output of a comparator that
continuously monitors both SMPS output voltages for
undervoltage conditions. PGDALL is actively held low
in shutdown (SHDN = GND), during soft-start, and soft-
shutdown, and when either SMPS is disabled (either
Figure 6. Power-Good and Fault Protection
interprets the MOSFET gates as “off” while charge actu-
ally remains. Use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps prevent
DL_ from being pulled up due to capacitive coupling from
the drain to the gate of the low-side MOSFETs when the
inductor node (LX_) quickly switches from ground to V
GD
GD
POWER-GOOD
0.9 x INT REF_
= C
), and additional board parasitics should not
RSS
), gate-to-source capacitance (C
V
Power-Good Output (PGDALL)
GS TH
6144
POR
CLK
(
0.7 x INT REF_
)
>
PROTECTION
V
IN
FAULT
⎛
⎜
⎝
C
C
1.11 x INT REF_
RSS
ISS
LATCH
FAULT
⎞
⎟
⎠
INTERNAL FB
ENABLE OVP
ENABLE UVP
FAULT
POWER-GOOD
GS
= C
ISS
23
IN
.