MAX8744ETJ+ Maxim Integrated Products, MAX8744ETJ+ Datasheet - Page 32

• Manufacturer Part Number: MAX8744ETJ+
• Description: IC CNTRLR PWR SUP QUAD 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8744ETJ+

• Applications: Controller, Notebook Computers
• Voltage - Input: 6 ~ 26 V
• Number Of Outputs: 4
• Voltage - Output: 3.3V, 5V, 1 ~ 26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Duty Cycle (max): 99 %
• Output Voltage: 3.315 V, 5.015 V, 2 V to 5.5 V
• Mounting Style: SMD/SMT
• Switching Frequency: 200 KHz, 300 KHz, 500 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Boost, Flyback, Forward
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(V
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.1µF ceramic capacitor.
Adjust the auxiliary linear regulator’s output voltage by
connecting a resistive divider between OUTA and ana-
log ground with the center tap connected to FBA
(Figure 1). Select R6 in the 10kΩ to 30kΩ range, and
calculate R5 with the following equation:
where V
The pass transistor must meet specifications for current
gain (β), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
where I
rent, V
and R
transistor’s base and emitter. Furthermore, the transis-
tor’s current gain increases the linear regulator’s DC
loop gain (see the LDOA Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 100 at the
maximum output current can be difficult to stabilize and
are not recommended. The transistor’s input capaci-
tance and input resistance also create a second pole,
which could be low enough to make the output unsta-
ble when heavily loaded.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the package’s power dissipation could
limit the useable maximum input-to-output voltage dif-
ferential. The maximum power dissipation capability of
High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
32
GS
______________________________________________________________________________________
= 5V). Using the above equation, the required
BE
BE
DRV
FBA
is the base-to-emitter voltage of the transistor,
is the pullup resistor connected between the
I
LOAD MAX
is the minimum guaranteed base drive cur-
= 1.0V.
C
BST
R
LDOA Design Procedure
(
5
=
=
R
)
200
13
Output Voltage Selection
6
=
⎛
⎜
⎝
nC
⎛
⎜
⎝
mV
V
I
V
DRV
OUTA
FBA
Transistor Selection
=
−
0 065
.
R
V
−
BE
BE
1
⎞
⎟
⎠
µF
⎞
⎟
⎠
β
MIN
the transistor’s package and mounting must exceed the
actual power dissipation in the device. The power dissi-
pation equals the maximum load current times the max-
imum input-to-output differential:
The MAX8744/MAX8745 linear-regulator controller uses
an internal transconductance amplifier to drive an exter-
nal pnp pass transistor. The transconductance amplifier,
the pass transistor, the base-to-emitter resistor, and the
output capacitor determine the loop stability.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
where V
transistor’s DC gain, and I
the base-to-emitter resistor (R
emitter resistor used in Figure 1 was chosen to provide
a 1mA bias current (I
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal ampli-
fier delay, the pass transistor’s input capacitance, and the
stray capacitance at the feedback node create additional
poles in the system, and the output capacitor’s ESR gen-
erates a zero. For proper operation, use the following
steps to ensure the linear-regulator stability:
1) First, calculate the dominant pole set by the linear
2) The pole caused by the internal amplifier delay is at
regulator’s output capacitor and the load resistor:
where C
iliary LDO and R
sponding to the maximum load current. The unity-
gain crossover of the linear regulator is:
approximately 1MHz:
T
is 26mV at room temperature, h
f
PWR = I
A
CROSSOVER
OUTA
V LDO
f
POLE LDO
(
PWR = I
LDOA Stability Requirements
f
)
is the output capacitance of the aux-
(
POLE(AMP)
LOAD(MAX)
=
BIAS
LOAD
⎛
⎜
⎝
5 5
)
V
= A
LOAD(MAX)
.
=
T
).
V
2π
is the load resistance corre-
V(LDO)
BIAS
⎞
⎟
⎠
⎛
⎜
⎝
C
1
≈ 1MHz
(V
OUTA LOAD
+
BE
INA
is the current through
I
BIAS FE
). The 680Ω base-to-
f
1
I
POLE(LDO)
LOAD
V
R
-V
CE
h
OUTA
⎞
⎟
⎠
FE
)
is the pass