L6731BTR STMicroelectronics, L6731BTR Datasheet - Page 6

• Manufacturer Part Number: L6731BTR
• Description: IC CTRLR ADJ STEP DOWN 16-TSSOP
• Manufacturer: STMicroelectronics

Specifications of L6731BTR

• Applications: Controller, DDR
• Voltage - Input: 1.8 ~ 14 V
• Number Of Outputs: 1
• Voltage - Output: Adjustable down to 0.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5099-2

Pin connections and functions
3
Figure 2.
Table 3.
6/24
Pin n.
1
2
3
4
5
6
7
Pin connections and functions
Pins connection ( Top view)
Pin functions
PGOOD
DDR-IN
SS/INH
V
COMP
SGND
Name
TTREF
FB
This pin is an open collector output and it is pulled low if the output voltage is not
within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up
this pin to V
This pin is connected to the output of an internal buffer that provides ½ of DDR-IN.
This pin can be connected to the V
with 10nF capacitor.
All the internal references are referred to this pin.
This pin is connected to the error amplifier inverting input. Connect it to V
the compensation network. This pin is also used to sense the output voltage in order
to manage the over voltage conditions and the PGood signal.
This pin is connected to the error amplifier output and is used to compensate the
voltage control feedback loop.
The soft-start time is programmed connecting an external capacitor from this pin and
GND. The internal current generator forces a current of 10 A through the capacitor.
When the voltage at this pin is lower than 0.5V the device is disabled.
By setting the voltage at this pin is possible to select the internal/external reference
and the switching frequency:
V
V
V
An internal clamp limits the maximum V
analog value present at this pin at the start-up when V
EAREF
EAREF
EAREF
VTTREF
PGOOD
DDR-IN
SS/INH
SGND
COMP
OCL
= 80%-95% of V
0-80% of V
= 95%-100% of V
FB
CCDR
with a 10K resistor to obtain a logical signal.
7
8
1
2
3
4
5
6
CCDR
HTSSOP16
CCDR
-> External Reference/F
CCDR ->
-> V
14
13
12
11
10
15
16
9
V
TTREF
REF
REF
Function
= 0.6V/F
= 0.6V/F
EAREF
input of the DDR memory itself. Filter to GND
VCC
VCCDR
LGATE
BOOT
HGATE
PHASE
OCH
PGND
at 2.5V (typ.). The device captures the
SW
SW
SW
=500KHz
=250KHz
=250KHz
CC
meets the UVLO threshold.
OUT
L6731B
through