SC418ULTRT Semtech, SC418ULTRT Datasheet - Page 19

• Manufacturer Part Number: SC418ULTRT
• Description: IC BUCK SYNC ADJ 20MLPQ
• Manufacturer: Semtech
• Series: EcoSpeed™, SmartDrive™r
• Type: Step-Down (Buck)r

Specifications of SC418ULTRT

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 5.5 V
• Frequency - Switching: 200kHz ~ 1MHz
• Voltage - Input: 3 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-MLPQ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Other names: SC418ULTRTTR

Applications Information (continued)
cycle. The switcher will shut off if VDDA falls below 2.7V.
VDDP does not have ULVO protection.
Note that the VDDA UVLO will not stop MOSFET switching
until the VDDA voltage falls to 2.7V. During this time the
gate driver voltages will track the VDDA supply. Not all
MOSFETs will operate or switch effectively at drive levels
of 2.7V. For this reason, it is not recommended to rely on
VDDA UVLO to shutdown the switcher unless the MOSFETs
are capable of operating with 2.7V drive.
LDO Regulator
The LDO output is programmable from 0.75V to 5.25V
using external resistors. The feedback pin (FBL) for the
LDO is regulated to 750mV. The LDO enable pin (ENL)
provides independent control. The LDO voltage can be
used to provide the bias voltage for the switching regula-
tor. When a separate source is used as the bias supply, the
LDO can be programmed to provide a different voltage.
The external resistor connections are shown in Figure 10.
The LDO output voltage is set by the following equation.
A minimum capacitance of 1μF referenced to AGND is
normally required at the output of the LDO for stability. If
the LDO is providing bias power to the device, then a
minimum 0.1μF capacitor referenced to AGND is required,
along with a minimum 1μF capacitor referenced to PGND
to filter the gate drive pulses. Refer to the PCB Layout
Guidelines section.
ENL Pin and VIN UVLO
The ENL pin also acts as the V
the switcher. The V
resistor divider at the VIN, ENL and AGND pins. The V
UVLO function has a typical threshold of 2.6V on the V
rising edge. The falling edge threshold is 2.4V.
VLDO
VLDO
Figure 10 — VLDO Resistor Divider
750
mV
IN
R
UVLO voltage is programmable via a
LDO1
1
R
R
LDO
LDO
IN
2
1
under-voltage lockout for
R
LDO2
To FBL pin
IN
IN
Timing is important when driving ENL with logic and not
implementing V
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the V
old and stays above 1V, then the switcher will turn off but
the LDO will remain on.
Note that it is possible to operate the switcher with the
LDO disabled, but the ENL pin must be below the logic
low threshold (0.4V maximum), otherwise the V
function will disable the switcher.
The table below summarizes the function of the ENL and
EN pins, with respect to the rising edge of ENL.
Figure 11 shows the ENL voltage thresholds and their
effect on LDO and Switcher operation.
high
high
high
low
low
low
EN
2.6V
2.4V
ENL low
threshold
(min 0.4V)
AGND
high, < 2.6V
high, < 2.6V
high, > 2.6V
high, > 2.6V
low, < 0.4V
low, < 0.4V
ENL
Figure 11 — ENL Thresholds
ENL voltage
IN
UVLO. The ENL pin must transition from
LDO on
Switcher on if EN = high
LDO on
Switcher off by VIN UVLO
LDO off
Switcher on if EN = high
LDO status
off
off
on
on
on
on
VIN UVLO hysteresis
Switcher status
IN
UVLO thresh-
SC418
off
on
off
off
off
on
IN
UVLO
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