L4974A STMicroelectronics, L4974A Datasheet - Page 4

• Manufacturer Part Number: L4974A
• Description: IC REG SW 3.5A 5.1V-40V 20-DIP
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L4974A

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 5.1 ~ 40 V
• Current - Output: 3.5A
• Frequency - Switching: 100kHz
• Voltage - Input: 15 ~ 50 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Power - Output: 1.3W
• Output Voltage: 40 V
• Output Current: 3.5 A
• Input Voltage: 15 V to 50 V
• Switching Frequency: 90 KHz to 110 KHz
• Operating Temperature Range: - 40 C to + 150 C
• Mounting Style: Through Hole
• Duty Cycle (max): 90 %
• No. Of Outputs: 1
• Power Dissipation Pd: 5W
• No. Of Pins: 20
• Filter Terminals: Through Hole
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6699-5; L4974A

L4974A
CIRCUIT OPERATION
The L4974A is a 3.5A monolithic stepdown switch-
ing regulator working in continuous mode realized in
the new BCD Technology. This technology allows
the integration of isolated vertical DMOS power tran-
sistors plus mixed CMOS/Bipolar transistors.
The device can deliver 3.5A at an output voltage ad-
justable from 5.1V to 40V and contains diagnostic
and control functions that make it particularly suit-
able for microprocessor based systems.
BLOCK DIAGRAM
The block diagram shows the DMOS power tran-
sistors and the PWM control loop. Integrated func-
tions include a reference voltage trimmed to 5.1V
feedforward control, pulse by pulse current limit,
thermal shutdown and finally the reset and power
fail circuit. The reset and power fail circuit provides
an output signal for a microprocessor indicating the
status of the system.
Device turn on is around 11V with a typical 1V hys-
terysis, this threshold porvides a correct voltage for
the driving stage of the DMOS gate and the hyste-
rysis prevents instabilities.
An external bootstrap capacitor charge to 12V by an
internal voltage reference is needed to provide cor-
rect gate drive to the power DMOS. The driving cir-
cuit is able to source and sink peak currents of
around 0.5A to the gate of the DMOS transistor. A
typical switching time of the current in the DMOS
transistor is 50ns. Due to the fast commutation
switching frequencies up to 200kHz are possible.
The PWM control loop consists of a sawtooth oscil-
lator, error amplifier, comparator, latch and the out-
put stage. An error signal is produced by comparing
the output voltage with the precise 5.1V 2% on chip
reference. This error signal is then compared with
the sawtooth oscillator in order to generate frixed
frequency pulse width modulated drive for the out-
put stage. A PWM latch is included to eliminate
multiple pulsing within a period even in noisy envi-
ronments.
The gain and stability of the loop can be adjusted by
4/22
2%, soft start, undervoltage lockout, oscillator with
an external RC network connected to the output of
the error amplifier. A voltage feedforward control
has been added to the oscillator, this maintains su-
perior line regulation over a wide input voltage
range. Closing the loop directly gives an output vol-
tage of 5.1V, higher voltages are obtained by insert-
ing a voltage divider.
At turn on, output overcurrents are prevented by the
soft start function (fig. 2). The error amplifier is in-
itially clamped by an external capacitor, Css, and al-
lowed to rise linearly under the charge of an internal
constant current source.
Output overload protection is provided by a current
limit circuit. The load current is sensed by a internal
metal resistor connected to a comparator. When the
load current exceeds a preset threshold, the output
of the comparator sets a flip flop which turns off the
power DMOS. The next clock pulse, from an internal
40kHz oscillator, will reset the flip flop and the power
DMOS will again conduct. This current protection
method, ensures a constant current output when the
system is overloaded or short circuited and limits the
switching frequency, in this condition, to 40kHz. The
Reset and Power fail circuit (fig. 4), generates an
output signal when the supply voltage exceeds a
threshold programmed by an external voltage di-
vider. The reset signal, is generated with a delay
time programmed by a external capacitor on the de-
lay pin. When the supply voltage falls below the
threshold or the output voltage goes below 5V, the
reset output goes low immediately. The reset output
is an open drain.
Fig. 4A shows the case when the supply voltage is
higher than the threshold, but the output voltage is
not yet 5V.
Fig. 4B shows the case when the output is 5.1V, but
the supply voltage is not yet higher than the fixed
threshold.
The thermal protection disables circuit operation
when the junction temperature reaches about
150 C and has a hysterysis to prevent unstable
conditions.