LP3907SQ-PXPP/NOPB National Semiconductor, LP3907SQ-PXPP/NOPB Datasheet - Page 29
![IC BUCK SYNC 1.5V/3.3V 24LLP](/photos/6/54/65470/pkg_sqa24a_sml.jpg)
LP3907SQ-PXPP/NOPB
Manufacturer Part Number
LP3907SQ-PXPP/NOPB
Description
IC BUCK SYNC 1.5V/3.3V 24LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Step-Down (Buck)r
Datasheet
1.LP3907SQ-JXQXNOPB.pdf
(46 pages)
Specifications of LP3907SQ-PXPP/NOPB
Topology
Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
Function
Any Function
Number Of Outputs
4
Frequency - Switching
2.1MHz
Voltage/current - Output 1
1.5V, 1A
Voltage/current - Output 2
3.3V, 600mA
Voltage/current - Output 3
2.5V, 300mA
W/led Driver
No
W/supervisor
No
W/sequencer
Yes
Voltage - Supply
2.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-LLP
Current - Output
300mA, 600mA, 1A
Voltage - Output
1.5V, 3.3V
Voltage - Input
2.8 ~ 5.5 V
Power - Output
1.43W
Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LP3907SQ-PXPPTR
I
I
The LP3907 features an I
two dedicated pins: SCL and SDA for I
spectively. Both signals need a pull-up resistor according to
the I
is clocked by the incoming SCL clock.
I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while the SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
2
2
2
C SIGNALS
C START AND STOP CONDITIONS
C Compatible Serial Interface
2
2
C specification. The LP3907 interface is an I
C session. START condition is defined as the SDA signal
2
C compatible serial interface, using
2
C clock and data re-
2
START and STOP Conditions
C slave that
I
2
C Signals: Data Validity
29
Signal timing specifications are according to the I
ification. The maximum bit rate is 400kbit/s. See I
cation from Philips for further details.
I
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
to HIGH while the SCL is HIGH. The
erates START and STOP bits. The I2C bus is considered to
be busy after START condition and free after STOP condition.
During data transmission, I
START conditions. First START and repeated START condi-
tions are equivalent, function-wise.
2
C DATA VALIDITY
30017816
30017817
2
C master can generate repeated
2
C master always gen-
2
www.national.com
C bus spec-
2
C specifi-