E-L6919ETR STMicroelectronics, E-L6919ETR Datasheet

Page 1

... The device assures a fast protection against load over current and load over/under voltage. An inter- nal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Cur- rent mode. ...

Page 2

... UGATE2 PHASE2 LGATE1, PHASE1, LGATE2, PHASE2 to PGND VID0 to VID4 All other pins to PGND V Sustainable Peak Voltage t < 20ns @ 600kHz phase UGATEx Pin Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002”Human Body Model” OTHER PINS Acceptance Criteria: “Normal Performance” THERMAL DATA ...

Page 3

... V Falling; V =5V CC CCDR V Rising CCDR V =12V CC V Falling CCDR V =12V CC OSC = OPEN OSC = OPEN; Tj 125 C I =5mA SINK OSC = OPEN OSC = OPEN OVP or UVP Active VID0, VID1, VID2, VID3, VID4 see Table1; FBR = V ; FBG = GND OUT VIDx = GND VIDx = OPEN COMP=10pF ...

Page 4

... L6919E ELECTRICAL CHARACTERISTICS (continued 12V ±15 70°C unless otherwise specified CC J Symbol Parameter DIFFERENTIAL CURRENT SENSING I , Bias Current ISEN1 I ISEN2 I Bias Current PGNDSx I , Bias Current at ISEN1 Over Current Threshold I ISEN2 I Active Droop Current FB GATE DRIVERS t High Side RISE Rise Time HGATE ...

Page 5

... The device automatically regulates 25mV higher than the Hammer specs avoiding the use of any external offset resistor Reference Schematic Vin GNDin HS1 L1 LS1 Output VID0 VID4 VID3 Voltage (V) 0 1.575 1 1 1.550 1 0 1.525 1 1 1.500 1 0 1.475 1 1 1.450 1 0 1.425 ...

Page 6

... PGNDS net in order to couple in common mode any picked-up noise. 14 PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up noise. 15 PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up noise ...

Page 7

... The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor. 23 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds and during soft start. It cannot be pulled-up above 5V. If not used may be left floating. 24 BOOT2 Channel 2 HS driver supply ...

Page 8

... In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships: R vs. GND vs. 12V Note that forcing into this pin, the device stops switching because no current is delivered to the oscillator. Figure 1. R vs. Switching Frequency OSC 14000 12000 10000 8000 ...

Page 9

... Internal pull-ups are PROG provided (realized with current generator up to 3.0V Typ); in this way, to program a logic "1" enough to leave the pin floating, while to program a logic "0" enough to short the pin to GND. Programming the " ...

Page 10

... The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac- itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with V = 12V ...

Page 11

... Introducing now the maximum ON time dependence with the delivered current (where T is the switching period T=1 0. – ON,MAX FB This linear dependence has a value at zero load of 0.80·T and at maximum current of 0.40·T typical and results in two different behaviors of the device SENSE PHASE I = ---------------------------------------------- INFO ...

Page 12

... OCP event is detected. This means that the average current delivered can slightly increase also in Over Current condition since the cur- rent ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the I bottom. The worst-case condition is when the ON time reaches its maximum value. ...

Page 13

... This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de- pendence of the output voltage on the load current As shown in figure 7, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (V tional to the output current ...

Page 14

... The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy on the output voltage when the RB Is used: eliminating it from the control loop causes the regulation error to be increased by the RB offset worsening the device performances. ...

Page 15

... OVP / UVP conditions. Power good output is forced low if the voltage sensed by VSEN is not within ±12% (Typ.) of the programmed value open drain output and it is enabled only after the soft start is finished (2048 clock cycles after start- up). During Soft-Start this pin is forced low. ...

Page 16

... Duty Cycle (V It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst case condition that happens for D = 0.25 and D = 0.75. The power dissipated by the input capacitance is then equal to: Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the high RMS value needed by the CPU power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor ...

Page 17

... Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the ap- plication of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage ...

Page 18

... COMP pin (See fig. 14). The current sharing control is a high bandwidth control loop allowing current sharing even during load transients. ...

Page 19

... The current sharing error is internally dominated by the voltage offset of Tran conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the cur- rent reading error is given by the following equation: Where I is the difference between one phase current and the ideal current (I ...

Page 20

... V The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes with a constant -20dB/dec slope with the desired crossover frequency transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the zero is fixed by ESR and the Droop resistance ...

Page 21

... Integrated power drivers reduce components count and interconnections between control functions and drivers, reducing the board space. Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor- rect implementation. Power Connections. These are the connections where switching and continuous current flows from the input supply towards the load. ...

Page 22

... High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if implemented the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess of 2A (30 mils wide is suggested) ...

Page 23

... Remote Buffer: The input connections for this components must be routed as parallel nets from the FBG/FBR pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load, will cause a non-optimum load reg- ulation, increasing output tolerance ...

Page 24

... FBG and FBR connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers JP3, JP4 and JP5. Local sense through the R7 is used for the regulation. ...

Page 25

... Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail that is used for the conversion. With an additional zener diode DZ1 a lower voltage can be derived to supply the mosfets driver if Logic level mosfet are used. In this case JP1 must be left open so that the HS driver is supplied with V ...

Page 26

... L6919E PCB AND COMPONENT LAYOUT Figure 23. PCB and Components Layouts (Dimensions: 10.8mm x 8.2mm) Component Side Internal SGND Plane 26/33 Internal PGND Plane Solder Side ...

Page 27

... CPU Power Supply 12V IN Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast reaction, this helps in reducing output and input capacitor. Inductance value is also reduced. A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compen- sation network. Considering the high output current, power conversion will start from the 12V bus. – ...

Page 28

... C24 100n L1, L2 0.8 U1 L6919E Q1, Q3 SUB85N03-04P Q2, Q4 SUB70N03-09BP D1, D2 STPS340U D3, D4 1N4148 S0,S4 Short S1,S2,S3 Open STATIC PERFORMANCES Figure 24 shows the demo board measured efficiency versus load current in steady state conditions without air- flow at ambient temperature. Figure 24. System Efficiency 28/ Ceramic ...

Page 29

... Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR. Figure 26 45A Load Transient Response Figure 27 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A). Figure 27. Dynamic VID Response 1 ...

Page 30

... L1, L2 0.8 U1 L6919E Q1, Q1a, Q3, Q3a SUB85N03-04P Q2, Q4 SUB70N03-09BP D1, D2 STPS340U D3, D4 1N4148 S0,S4 Short S1,S2,S3 Open STATIC PERFORMANCES Figure 28 shows the demo board measured efficiency versus load current in steady state conditions without air- flow at ambient temperature. Figure 28. System Efficiency 30/ ...

Page 31

... Output Current [A] Figure 30 shows the system response to a load transient from 3A to 45A. The output voltage is contained in the ±50mV range. Additional output capacitors can help in reducing the initial voltage spike mainly due to the ESR. Figure 30 45A Load Transient Response Figure 31 shows the system response to a VID transient from 1.200V to 0.800V and vice versa at minimum load (3A). ...

Page 32

... C 0 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 7.6 0.291 L 0.4 1.27 0.016 S 8 (max.) 32/33 inch MECHANICAL DATA TYP. MAX. 0.104 0.012 0.019 0.013 0.020 0.713 0.419 0.050 0.65 0.299 0.050 OUTLINE AND SO28 ...

Page 33

... The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © ...