LTC1709EG Linear Technology, LTC1709EG Datasheet - Page 18

• Manufacturer Part Number: LTC1709EG
• Description: IC REG SW 2PH SYNC STPDWN 36SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1709EG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 3.5 V
• Current - Output: 3A
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

APPLICATIO S I FOR ATIO
LTC1709
floated or connected to V
series diode is used to prevent the digital inputs from
being damaged or clamped if they are driven higher than
V
V
normally connected to INTV
other sources. If it is driven from another source, that
source MUST be in the range of 2.7V to 5.5V and MUST be
alive prior to enabling the LTC1709.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) Run/Shut-
down, 2) soft-start and 3) a defeatable short-circuit latchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit I
extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5 A) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.
An internal 1.2 A current source charges up the soft-start
capacitor, C
1.5V, the controller is permitted to start operating. As the
voltage on RUN/SS increases from 1.5V to 3.0V, the
internal current limit is increased from 25mV/R
75mV/R
taking an additional 1.25s/ F to reach full current. The
output current thus ramps up slowly, reducing the starting
surge current required from the input power supply. If
RUN/SS has been pulled all the way to ground there is a
delay before starting of approximately:
The time for the output current to ramp up is then:
By pulling the RUN/SS pin below 0.8V the LTC1709 is put
into low current shutdown (I
can be driven directly from logic as shown in Figure 6.
18
BIAS
BIAS
t
t
DELAY
RAMP
. The digital inputs accept CMOS voltage levels.
TH(MAX)
is the supply voltage for the VID section. It is
SENSE
3
SS
1 2
1 5
. The latchoff timer prevents very short,
V
. The output current limit ramps up slowly,
.
1 2
. When the voltage on RUN/SS reaches
.
.
V
A
1 5
.
A
U
C
SS
V
C
BIAS
SS
U
1 25
Q
to get a digital high input. The
.
CC
< 40 A). The RUN/SS pins
1 25
s
.
but can be driven from
/
s
W
F C
/
F C
SS
SS
U
SENSE
to
Diode D1 in Figure 6 reduces the start delay but allows C
to ramp up slowly providing the soft-start function. The
RUN/SS pin has an internal 6V zener clamp (see Func-
tional Diagram).
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor, C
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltage falls to less than 70% of its nominal value after C
reaches 4.1V, C
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of C
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:
If the overload occurs after start-up, the voltage on C
continue charging and will provide additional time before
latching off:
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, R
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci-
tor during a severe overcurrent and/or short-circuit con-
dition. When deriving the 5 A current from V
figure, current latchoff is always defeated. Diode connect-
ing this pull-up resistor to INTV
t
t
LO1
LO2
3.3V OR 5V
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
(C
(C
SS
SS
SS
D1
Figure 6. RUN/SS Pin Interfacing
, the controller will be shut down until the
• 0.6V)/(1.2 A) = 5 • 10
• 3V)/(1.2 A) = 2.5 • 10
SS
V
IN
begins discharging on the assumption
R
SS
SS
*
RUN/SS
, is used initially to limit the inrush
C
SS
SS
, to the RUN/SS pin as
D1*
INTV
5
6
(C
(C
CC
R
SS
SS
SS
*
CC
)
)
RUN/SS
IN
, as in
as in the
1709 F06
C
SS
SS
will
SS
SS