LTC3728EG Linear Technology, LTC3728EG Datasheet - Page 29

• Manufacturer Part Number: LTC3728EG
• Description: IC SW REG SYNC STP-DN DUAL28SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3728EG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 250kHz ~ 550kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3728. These items are also illustrated graphically
in the layout diagram of Figure 10. Figure 11 illustrates
the current waveforms present in the various branches
of the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connec-
tion at C
for the two channels as it can cause a large resonant
loop.
R1
R3
IN
? Do not attempt to split the input decoupling
R2
R4
INTV
3.3V
CC
f
IN
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram
RUN/SS1
SENSE1
SENSE1
V
PLLFLTR
PLLIN
FCB
I
SGND
3.3V
I
V
SENSE2
SENSE2
TH1
TH2
OSENSE1
OSENSE2
OUT
+
–
LTC3728
–
+
RUN/SS2
BOOST1
BOOST2
EXTV
PGOOD
INTV
PGND
SW1
SW2
BG1
BG2
TG1
TG2
V
CC
CC
IN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2. Are the signal and power grounds kept separate? The
3. Do the LTC3728 V
R
PGOOD
combined LTC3728 signal ground pin and the ground
return of C
(–) terminals. The path formed by the top N-channel
MOSFET, Schottky diode and the C
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
to the (+) terminals of C
be connected between the (+) terminal of C
PU
C
C
C
B1
B2
INTVCC
V
(<7V)
PULL-UP
INTVCC
C
VIN
V
R
IN
M1
IN
M3
OSENSE
must return to the combined C
M2
M4
L1
C
L2
IN
OUT
pins resistive dividers connect
? The resistive divider must
R
R
SENSE
SENSE
C
C
D1
OUT1
OUT2
D2
IN
LTC3728
capacitor should
3728 F10
V
GND
V
OUT1
OUT2
OUT
29
3728fg
and
OUT