LTC3728EUH#TR Linear Technology, LTC3728EUH#TR Datasheet - Page 8

• Manufacturer Part Number: LTC3728EUH#TR
• Description: IC SW REG SYNC STP-DN DUAL 32QFN
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3728EUH#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 250kHz ~ 550kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Other names: LTC3728EUHTR

LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS
PIN FUNCTIONS
RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combination
of soft-start, run control inputs and short-circuit detection
timers. A capacitor to ground at each of these pins sets the
ramp time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overcurrent
protection is also invoked via this pin as described in the
Applications Information section.
SENSE1
Input to the Differential Current Comparators. The I
voltage and controlled offsets between the SENSE
SENSE
trip threshold.
SENSE1
Input to the Differential Current Comparators.
V
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Lowpass
Filter is Tied to This Pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
8
OSENSE1
+
+
–
pins in conjunction with R
, SENSE2
, SENSE2
, V
3.50
3.45
3.20
3.40
3.35
3.30
3.25
OSENSE2
–50
Undervoltage Lockout
vs Temperature
–25
+
–
(Pins 4, 12/Pins 1, 9): Receives the
(Pins 2, 14/Pins 30, 12): The (+)
(Pins 3, 13/Pins 31, 11): The (–)
0
TEMPERATURE (°C)
25
G Package/UH Package
50
SENSE
75
100
set the current
3728 G29
125
TH
–
and
pin
with 50kΩ. The phase-locked loop will force the rising
top gate signal of controller 1 to be synchronized with
the rising edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input.
This input acts on both controllers and is normally used
to regulate a secondary winding. Pulling this pin below
0.8V will force continuous synchronous operation.
I
and Switching Regulator Compensation Point. Each as-
sociated channels’ current comparator trip point increases
with this control voltage.
SGND (Pin 9/Pin 6): Small Signal Ground common to
both controllers, must be routed separately from high
current grounds to the common (–) terminals of the
C
3.3V
pable of supplying 10mA DC with peak currents as high
as 50mA.
NC (Pins 10, 16, 29, 32 UH Package Only): No Connect.
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to
the sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky rectifi ers and the (–) terminal(s)
of C
TH1,
OUT
IN
OUT
I
capacitors.
.
TH2
(Pin 10/Pin 7): Output of a linear regulator ca-
(Pins 8, 11/Pins 5, 8): Error Amplifi er Output
3.0
2.5
2.0
1.0
4.5
4.0
3.5
1.5
0.5
0
–50
Shutdown Latch Thresholds
vs Temperature
–25
0
TEMPERATURE (°C)
THRESHOLD
LATCHOFF
25
LATCH ARMING
50
75
100
3728 G30
125
3728fg